BEOL, Integration, PECVD, RIE, Low-k, clean

1. Sunil Kumar Singh
25 Ridgewood Drive Phone: (518) 222-0902
Mechanicville, NY, 12118 Email: sunil.iitb@gmail.com
PROFESSIONAL PROFILE
• Experienced semiconductor industry professional with doctoral level skills & 15 years of
experience in processes (PECVD, spin coating, RIE, Wet Clean), integration & product innovation
for emerging technologies, while working with & leading global and cross-cultural integration and
R&D teams.
• 15 years’ experience in BEOL Process Integration/Technology Development in Semiconductor
R&D and Manufacturing. Excellent knowledge of integrated module interactions, SPC, PCP,
implications on electrical parameters, defectivity, manufacturability, yield, and reliability.
• More than 15 years of experience in Materials Sciences R&D with documented success of new
product and technology development (15+ publications, 9 issued, 1 trade secret and 12 filed
patents).
WORK EXPERIENCE
07/2012 – Present, GLOBALFOUNDRIES, Malta, NY, USA
Member of Technical Staff (MTS) BEOL Integration
• Successfully leading 64nm pitch BEOL module to achieve BEOL-D0 targets for 128MB 70% SRAM
yield. Coordinated with CVD, PVD, Photo lithography, RIE (etch), wet clean and CMP team to
reduce overall NDDcWb from 19.10 to <0.34.
• Leading & mentoring BEOL integration team as technology champion and managerial back-up.
Actively involved in 14nm Ramp; Providing solutions and executing on multiple CIP’s to resolve
major yield detractors across 3 technologies; 14, 20 & 28nm.
• Successfully Qualify 64nm pitch BEOL reliability (EM, TDDB and SM).
• Leading task force to resolve line excursion/process drift.
• Developed Co liner/Cap integration scheme for 14LLP technology for device performance
improvement.
• Enhancing company’s technical vitality through conference lectures, invention disclosure & patent
07/2009 – 07/2012, TSMC, Hsinchu, Taiwan
Technical manager/ Etch lead/Project Manager
• Successfully developed and implemented less damage (12% RC reduction) etch profile for TSMC
20nm node technology.
• Successfully lead & managed wet cleaning R&D projects as the chief scientist while working
closely with customers in accessing industry demands and defining company’s cleaning
technology roadmap for advanced technology nodes (28 and 20 nm and below).
• Developed new concepts and fundamental technology for resist stripping and cleaning.
• Lead for next generation path finding team for Double/multiple/EUV/DSA patterning and base
line setup and qualification.
• Successfully achieved challenging milestones of short and long term Joint Development Programs
(JDP) with IMEC.
• Enhancing company’s technical vitality through conference lectures, invention disclosure & patent
07/2006 – 07/2009, TSMC, Hsinchu, Taiwan
Principal Engineer/ PECVD low-k
• Successfully developed PECVD based XLK/ULK materials (k~2.0/2.4/2.55) for current and new
generation technology.
• Successfully developed and integrate air gap between metal trench line to improve RC delay and
device speed.
• Worked with UV tool vendors to develop UV curing process to improve porogen removal
efficiency and ULK mechanical properties.
For GLOBALFOUNDRIES Internal use only.
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2. Sunil Kumar Singh
• Ownership of AMAT producer tool for low-k dep and cure. Daily basis tool monitor and process
improvement.
TECHNICAL SKILLSET
 Characterization: TEM/SEM, XPS, FTIR, AES, EELS, AFM, IR, XrD, SIMS, Adhesion test,
hardness test; Electrical: Hg probe for Dielectric, CV and IV measurement.
 Semiconductor Equipment: Hands on knowledge of RIE tools (LAM and TEL), PECVD, spin
coating, wet clean, PVD, UV/thermal curing. Working knowledge of Coat, Develop, & Bake
tools, BFI & DFI Inspection, CDSEM, thickness measurement.
 System tool: Si-View, ECOP, ACE- XP, Mask review, i-EDA, JMP, Wafer, Window, Ms-office, Origin, Shiny, SPC
 General: SAP based Project Management tools, DOE & SPC tools, FMEA, Factory Systems.
EDUCATION
May 2006 Indian Institute of Technology (IITB) Mumbai, India
Doctorate of Philosophy (PhD), Materials Science and Technology
June 2001 Indian Institute of Technology, BHU Varanasi, India
Master of Technology (M. Tech.), Materials Science and Technology
APPROVED AWARDED
 Reduced capacitance interlayer structures and fabrication methods, US 9,142,451
 Methods and structures for back end of line integration, US 9,117,822
 Interconnection wires of semiconductor devices, US 9,093,501
 Addition of carboxyl groups plasma during etching for interconnect reliability enhancement, US 8,901,007
 Etch damage and ESL free dual damascene metal interconnect, US 8,652,962
 Air gap for interconnect application, US 7,682,963
 Forming interconnect structure with polymeric layer and resulting device, US 20150325525
 A method of depositing an amorphous-SiC: H barrier layer on a low k dielectric material layer, India 223221
 A method of treating a low k dielectric material layer coated on a Si substrate, India 231216
RELEVANT PUBLICATIONS
 Process variation challenges and resolution in the negative-tone develop double patterning for 20nm and below
technology node, S. S. Mehta, L. K. Ganta, V. Chauhan, Y. Wu, S. K. Singh, Chia Ann, L. Subramany, C. Higgins, B.
Erenturk, R. Srivastava, P. Singh, H. P. Koh, D. Cho, SPIE-2015
 A novel LWR reduction approach to enhance reliability performance in ultra-thin barrier/porous low-k (K<2.4)
interconnect, C. W. Lu, T. J. Tsai, Y. S. Chang, C. H. Tsai, S. K. Singh, T. M. Huang, H. C. Yao, C. J. Lee, T.I. Bao, S. L.
Shue & C.H. Yu, IITC-2012.
 Low Damage Etch Approach for Next Generation Cu Interconnect, S. K. Singh, C. J. Lee , C. H. Tsai, T. M. Huang, C. W.
Lu, T. J. Tsai, Y. S. Chang, T.I. Bao, S. L. Shue & C.H. Yu, IITC-2011.
 Maintaining Cu metal integrity on low-k IMDs with a nanometer thick a-SiC:H film obtained by HWCVD, S.K. Singh, A.A.
Kumbhar and R.O. Dusane, Thin Solid Films, Volume 516, Issue 5, 785, 2008.
 Repairing plasma-damaged low-k HSQ films with trimethylchlorosilane treatment, S.K. Singh, A. A.Kumbhar and R.O.
Dusane, Materials Science and Engineering: B, Volume 127, Issue 1, 29, 2006,
 Resisting oxygen plasma damage in low-k hydrogen silsesquioxane films by hydrogen plasma treatment, S.K. Singh,
A.A. Kumbhar and R.O. Dusane, Materials Letters, Volume 60, Issues 13-14, 1579, 2006.
 Potential of Cat-CVD deposited a-SiC:H as diffusion barrier layer on low-k HSQ films for ULSI, S. K. Singh, A. A.
Kumbhar, M. Kothari and R.O. Dusane, Thin Solid Films, Volume 501, Issues 1-2, 318, 2006.
 Hot-wire chemical-vapor-deposited nanometer range a-SiC:H diffusion barrier films for ultra large-scale integrated
application, S. K. Singh, A. A. Kumbhar, R. O. Dusane, W. Bock, JVSTB, Volume: 24(2), 543, 2006.
 Enhancement of moisture resistance of spin-on low-k HSQ films by hot wire generated atomic hydrogen treatment, A. A.
Kumbhar, S. K. Singh and R.O. Dusane, Thin Solid Films, Volume 501, Issues 1-2, 329, 2006
 Further insights into the mechanism of hydrogen-plasma surface passivation of low-dielectric constant hydrogen
silsesquioxane (HSQ), S.K. Singh, A. A. Kumbhar, R. O. Dusane, W. Bock, Journal of the Korean Physical society,
vol. 49(3), 1312, 2006.
 The Effect of O2 Plasma treatment on Low Dielectric Constant HSQ Films, S. K. Singh, A. A. Kumbhar and R. O. Dusane,
Workshop on Plasma Surface Engineering, BARC, 23-25 Sept. 2004.
For GLOBALFOUNDRIES Internal use only.
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3. Sunil Kumar Singh
 Anhydrous silanization and antibody immobilization on hotwire CVD deposited silicon oxynitride films, M. Joshi, S. K.
Singh, B. Swain, S. B. Patil, R. O. Dusane, R. Rao, S. Mukherji, IEEE INDICON, 538, 2004.
Effect of thermal annealing and plasma treatment on the structural and electrical properties of low-k HSQ films, A.
Kumbhar, S. K. Singh, A. Srivastav and R. O. Dusane, Proc. 12th IWPSD, Vol. 1, 268, 2003.
AVAILABLE FOR NATIONWIDE RELOCATION & INTERNATIONAL TRAVEL
For GLOBALFOUNDRIES Internal use only.
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