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Parallel Computer Model
Outline
 Multi-vector Computer
 Description
 Advantages
 Architecture
 Vector supercomputers
 Memory-to-memory
 Register-to-register
 SIMD Computer
Description of Vector Processors
Advantages of Vector Processors
Architecture of a Vector Supercomputers
Architecture of a Vector Supercomputers(cont.)
 Often build on top of a scalar processor
 Vector processor is attached to the scalar processor as an optio
nal feature
 Program and data are first loaded into the main memory throug
h a host computer
 All instructions are first decoded by the scalar control unit. If th
e decoded instruction is a scalar operation or a program control
then directly executed by the scalar processor using the scalar f
unctional pipelines
 If the instruction is decoded as a vector operation then sent to t
he vector control unit(VCU). VCU supervise the flow of vector d
ata between the main memory and vector functional pipelines
 Two pipeline vector supercomputer models
 Register-to-register
 Memory-to-memory
Vector Processor Architectures
Vector Processor Architectures (cont.)
Components of Vector Processors
SIMD Supercomputers
Fig. : Operational Model of SIMD computers
SIMD Machine Model
 An operational model of an SIMD computer is s
pecified by a 5-tuple: M = (N, C, I, M, R) where
 N is the number of processing elements (PEs)
 C is the set of instructions directly executed by the
CU, including scalar and program flow control instru
ctions
 I is the set of instructions broadcast by the CU to all
PEs for parallel execution
 M is the set of masking schemes, where each mask
partitions the set of PEs into enabled and disabled s
ubsets
 R is the set of data-routing functions, specifying vari
ous patterns to be setup in the interconnection netw
ork for inter-PE communication
Questions?
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Lec 3 (parallel computer model)

  • 2. Outline  Multi-vector Computer  Description  Advantages  Architecture  Vector supercomputers  Memory-to-memory  Register-to-register  SIMD Computer
  • 4. Advantages of Vector Processors
  • 5. Architecture of a Vector Supercomputers
  • 6. Architecture of a Vector Supercomputers(cont.)  Often build on top of a scalar processor  Vector processor is attached to the scalar processor as an optio nal feature  Program and data are first loaded into the main memory throug h a host computer  All instructions are first decoded by the scalar control unit. If th e decoded instruction is a scalar operation or a program control then directly executed by the scalar processor using the scalar f unctional pipelines  If the instruction is decoded as a vector operation then sent to t he vector control unit(VCU). VCU supervise the flow of vector d ata between the main memory and vector functional pipelines  Two pipeline vector supercomputer models  Register-to-register  Memory-to-memory
  • 9. Components of Vector Processors
  • 10. SIMD Supercomputers Fig. : Operational Model of SIMD computers
  • 11. SIMD Machine Model  An operational model of an SIMD computer is s pecified by a 5-tuple: M = (N, C, I, M, R) where  N is the number of processing elements (PEs)  C is the set of instructions directly executed by the CU, including scalar and program flow control instru ctions  I is the set of instructions broadcast by the CU to all PEs for parallel execution  M is the set of masking schemes, where each mask partitions the set of PEs into enabled and disabled s ubsets  R is the set of data-routing functions, specifying vari ous patterns to be setup in the interconnection netw ork for inter-PE communication