The ever increasing demand to transfer data pushes the semiconductor industry to develop faster wired, wireless or optical interfaces (>20 Gbps). To meet those speeds, chip designers need to limit the parasitic capacitance of the on-chip ESD protection clamps. When traditional ESD concepts are not good enough, they need special analog I/O circuits like the proprietary solutions made available by Sofics.

1. Your Benefits
Proven technology gives you first time right designs
Sofics ESD technology has been included in 4500+ mass-produced IC designs, corresponding to
millions of wafers. The solutions have successfully been transferred to advanced CMOS and FinFET
technology nodes.
Broad solution spectrum gives you more options
Sofics has ESD solutions for the different power domains and for every type of interface. The clamps
are used in Analog I/O’s and can be used to protect digital I/O’s. The technology can be easily
customized to fit various requirements.
Beyond standard performance boosts your competitive advantage
Sofics creates ESD clamps with ultra-low parasitic capacitancefor highspeed interfaces like 112Gbps.
Clamps can be scaled to high ESD robustness like 8kV HBM. Sofics solutions add low stand-by leakage
and if needed can tolerate a higher voltage.
CONTACT SOFICS
bd@sofics.mail.com
www.sofics.com
SOFICS BVBA
©2019
ULTRA-LOW CAPACITANCE
I/O FOR FinFET GHz OR Gbps ICs
The ever increasing demand to transfer data pushes the semiconductor
industry to develop faster wired, wireless or optical interfaces (>20 Gbps).
To meet those speeds, chip designers need to limit the parasitic capacitance of the
on-chip ESD protection clamps. When traditional ESD concepts are not good enough,
they need special analog I/O circuits like the proprietary solutions made available by Sofics.
Working on a GHz or Gbps IC?
Get a low-cap esd cell for free
For selected integrated circuit projects, Sofics makes available,
free-of-charge, a low capacitance ESD solution capable of 1kV
HBM ANSI STM5.1 ESD performance between signal and supply
connections.
GDSII layout, description, datasheet, connection guidelines
are available for selected CMOS or FinFET nodes, and actual IC
projects taping out by or before 2020/12/31.
VALID ONLY
FOR SELECTED
IC PROJECTS
https://www.sofics.com/index.php?view=sofics-serdes