This presentation gives you complete detail about TMS320C5X digital processor.

1. TMS320C5X
DIGITAL SIGNAL PROCESSOR

2. Types of Digital Signal Processors
FIXED POINT
- Fixed-point DSPs are designed to
represent and manipulate integers via
a minimum of 16 bits, yielding up to
65,536 possible bit patterns ( )
FLOATING POINT
- Floating-point DSPs represent and
manipulate rational numbers via a
minimum of 32 bits, yielding up to
4,294,967,296 possible bit pattern( )216 232
You can read more about these types here

3. TMS320 Family
The TMS320 family consists of eight generations: the ’C1x, ’C2x, ’C2xx, ’C5x, and
’C54x are fixed-point, the ’C3x and ’C4x are floating-point, and the ’C8x is a
multiprocessor
As the generation of the processors increases the performance increases.
But the variation in the type of processor varies the performance.
Considering the performance
Multiprocessor > Floating point > Fixed point

4. TMS320
’C8x
’C3x < ’C4x
’C1x<’C2x< ’C2xx<’C5x
Multiprocessor
Floating Point
Fixed Point
Performanceincreases

5. Features
• Speed:
20-/25-/35-/50-ns single-cycle fixed-point instruction execution time
• Power:
- 3.3-V and 5-V
• Central processing unit (CPU):
- Central arithmetic logic unit (CALU)
- 16-bit Parallel Logic unit (PLU)
- Dedicated auxiliary register arithmetic unit (ARAU) for indirect addressing
- Eight auxiliary register

6. Architecture

7. ’C5x Functional
Block Diagram

8. Central Processing Unit(CPU)
The ’C5x CPU consists of five elements:
• Central arithmetic logic unit (CALU)
• Parallel logic unit (PLU)
• Auxiliary register arithmetic unit (ARAU)
• Memory-mapped registers
• Program controller

9. Central Arithmetic Logic Unit (CALU)
The CPU uses the CALU to perform 2s-complement arithmetic
Parallel Logic Unit(PLU)
The PLU performs Boolean operations or the bit manipulations required of high-speed
controllers
Auxiliary Register Arithmetic Unit (ARAU)
Calculates indirect addresses by using inputs from the auxiliary registers (ARs), index
register (INDX), and auxiliary register compare register (ARCR).

10. Memory-Mapped Register
Used for indirect data address pointers, temporary storage, CPU status and control,
or integer arithmetic processing through the ARAU
Program Controller
Contains logic circuitry that decodes the operational instructions, manages the
CPU pipeline, stores the status of CPU operations, and decodes the conditional
operations.
-Program counter
-Status and control registers
-Hardware stack
-Address generation logic
-Instruction register

11. Bus Structure
The ’C5x architecture is built around four major buses:
• Program bus (PB)
• Program address bus (PAB)
• Data read bus (DB)
• Data read address bus (DAB)

12. On-Chip Memory
To aid in system performance and integration of processor on-chip memory is
added. In ’C5x there are three types of On-Chip Memory
• Program read-only memory (ROM)
• Data/program dual-access RAM (DARAM)
• Data/program single-access RAM (SARAM)

13. On-Chip Peripherals
• Clock generator
• Hardware timer
• Software-programmable wait-state generators
• Parallel I/O ports
• Host port interface (HPI)
• Serial port
-General-purpose serial port
-Buffered serial port (BSP)
-Time-division multiplexed (TDM) serial port
• User-maskable interrupts

14. Advantages of ’C5
• Architectural design of TMS320 is enhanced for increased performance and
versatility
• Advanced integrated-circuit processing technology for increased performance
and low power consumption
• Source code compatibility with ’C1x, ’C2x, and ’C2xx DSPs for fast and easy
performance upgrades
• Enhanced instruction set for faster algorithms and for optimized high-level
language operation
• Reduced power consumption and increased radiation hardness because of new
static design tech
More about TMS320C5X

15. M Sasidhar