Carbon nanotube field-effect transistor - Wikipedia.pdf

Carbon nanotube
field-effect transistor
A carbon nanotube field-effect transistor
(CNTFET) is a field-effect transistor that
utilizes a single carbon nanotube or an
array of carbon nanotubes as the channel
material instead of bulk silicon in the
traditional MOSFET structure. First
demonstrated in 1998, there have been
major developments in CNTFETs
since.[1][2]

According to Moore's law, the dimensions
of individual devices in an integrated
circuit have been decreased by a factor of
approximately two every two years. This
scaling down of devices has been the
driving force in technological advances
since the late 20th century. However, as
noted by ITRS 2009 edition, further scaling
down has faced serious limits related to
fabrication technology and device
Introduction and background
A diagram showing that a carbon nanotube is essentially rolled up graphene

performances as the critical dimension
shrunk down to sub-22 nm range.[3] The
limits involve electron tunneling through
short channels and thin insulator films, the
associated leakage currents, passive
power dissipation, short channel effects,
and variations in device structure and
doping.[4] These limits can be overcome to
some extent and facilitate further scaling
down of device dimensions by modifying
the channel material in the traditional bulk
MOSFET structure with a single carbon
nanotube or an array of carbon nanotubes.

Electronic structure of
carbon nanotubes
Graphene atomic structure with a translational vector T and a chiral vector Ĉh of a CNT
One-dimensional energy dispersion relations for (a) (n,m)=(5,5) metallic tube, (b) (n,m)=(10,0) semiconducting tube.

To a first approximation, the exceptional
electrical properties of carbon nanotubes
can be viewed as inherited from the
unique electronic structure of graphene,
provided the carbon nanotube is thought
of as graphene rolled up along one of its
Bravais lattice vectors Ĉh to form a hollow
cylinder.[5] [6] [7] In this construction,
periodic boundary conditions are imposed
over Ĉh to yield a lattice of seamlessly
bonded carbon atoms on the cylinder
surface.[8]
Thus, the circumference of such a carbon
nanotube can be expressed in terms of its
rollup vector: Ĉh=nâ1+mâ2 that connects

two crystallographically equivalent sites of
the two-dimensional graphene sheet. Here
and are integers and â1 and â2 are
primitive lattice vectors of the hexagonal
lattice. Therefore, the structure of any
carbon nanotube can be described by an
index with a pair of integers that
define its rollup vector.[6] In terms of the
integers , the nanotube diameter
and the chiral angle are given by:
;
and, ,
where is the C—C bond distance.
Differences in the chiral angle and the
diameter cause the differences in the

properties of the various carbon
nanotubes. For example, it can be shown
that an carbon nanotube is
metallic when ,[5] is a small band
gap semiconductor when
and ,[6] [7] and is a moderate band
gap semiconductor when
,[6] [7] where is an integer.
These results can be motivated by noting
that periodic boundary conditions for 1D
carbon nanotubes permit only a few wave
vectors to exist around their
circumferences. Metallic conduction could
be expected to occur when one of these
wave vectors passes through the K-point

of graphene’s 2D hexagonal Brillouin zone,
where the valence and conduction bands
are degenerate.
This analysis, however, neglects the
effects of curvature caused by rolling up
the graphene sheet that converts all
nanotubes with to small
band gap semiconductors,[6] [7] with the
exception of the armchair tubes ( )
that remain metallic.[5] Although the band
gaps of carbon nanotubes with
and are relatively
small, some can still easily exceed room
temperature, if the nanotube diameter is
about a nanometer.[9] [10]

The band gaps of semiconducting
carbon nanotubes with
depend predominately on their diameters.
In fact, according to a single-particle tight-
binding description of the electronic
structure of these nanotubes
[11] where is the
nearest-neighbor hopping matrix element.
That this result is an excellent
approximation so long as is a lot
less than one has been verified both by all-
electron first principles local density
functional calculations[12] and
experiment.[13]

Scatter plots of the band gaps of carbon
nanotubes with diameters up to three
nanometers calculated using an all
valence tight binding model that includes
curvature effects appeared early in carbon
nanotube research[9] and were reprinted in
a review.[14]
A carbon nanotube’s bandgap is directly
affected by its chiral angle and diameter. If
those properties can be controlled, CNTs
would be a promising candidate for future
nano-scale transistor devices. Moreover,
because of the lack of boundaries in the
Motivations for transistor
applications

perfect and hollow cylinder structure of
CNTs, there is no boundary scattering.
CNTs are also quasi-1D materials in which
only forward scattering and back
scattering are allowed, and elastic
scattering means that free paths in carbon
nanotubes are long, typically on the order
of micrometers. As a result, quasi-ballistic
transport can be observed in nanotubes at
relatively long lengths and low fields.[15]
Because of the strong covalent carbon–
carbon bonding in the sp2 configuration,
carbon nanotubes are chemically inert and
are able to transport large electric
currents. In theory, carbon nanotubes are
also able to conduct heat nearly as well as

diamond or sapphire, and because of their
miniaturized dimensions, the CNTFET
should switch reliably using much less
power than a silicon-based device.[16]
There are many types of CNTFET devices;
a general survey of the most common
geometries are covered below.
Back-gated CNTFETs
Device fabrication
Top view
Side view

The earliest techniques for fabricating
carbon nanotube (CNT) field-effect
transistors involved pre-patterning parallel
strips of metal across a silicon dioxide
substrate, and then depositing the CNTs
on top in a random pattern.[1][2] The
semiconducting CNTs that happened to
fall across two metal strips meet all the
requirements necessary for a rudimentary
field-effect transistor. One metal strip is
the "source" contact while the other is the
"drain" contact. The silicon oxide substrate
can be used as the gate oxide and adding
Top and side view of a silicon back-gated CNTFET. The CNTFET consists of carbon nanotubes deposited on a silicon
oxide substrate pre-patterned with chromium/gold source and drain contacts.

a metal contact on the back makes the
semiconducting CNT gateable.
This technique suffered from several
drawbacks, which made for non-optimized
transistors. The first was the metal
contact, which actually had very little
contact to the CNT, since the nanotube
just lay on top of it and the contact area
was therefore very small. Also, due to the
semiconducting nature of the CNT, a
Schottky barrier forms at the metal–
semiconductor interface,[17] increasing the
contact resistance. The second drawback
was due to the back-gate device geometry.
Its thickness made it difficult to switch the

devices on and off using low voltages, and
the fabrication process led to poor contact
between the gate dielectric and CNT.[18]
Top-gated CNTFETs
Eventually, researchers migrated from the
back-gate approach to a more advanced
top-gate fabrication process.[18] In the first
The process for fabricating a top-gated CNTFET.

step, single-walled carbon nanotubes are
solution deposited onto a silicon oxide
substrate. Individual nanotubes are then
located via atomic force microscope or
scanning electron microscope. After an
individual tube is isolated, source and
drain contacts are defined and patterned
using high resolution electron beam
lithography. A high temperature anneal
step reduces the contact resistance by
improving adhesion between the contacts
and CNT.[19] A thin top-gate dielectric is
then deposited on top of the nanotube,
either via evaporation or atomic layer
deposition. Finally, the top gate contact is

deposited on the gate dielectric,
completing the process.
Arrays of top-gated CNTFETs can be
fabricated on the same wafer, since the
gate contacts are electrically isolated from
each other, unlike in the back-gated case.
Also, due to the thinness of the gate
dielectric, a larger electric field can be
generated with respect to the nanotube
using a lower gate voltage. These
advantages mean top-gated devices are
generally preferred over back-gated
CNTFETs, despite their more complex
fabrication process.

Wrap-around gate CNTFETs
Wrap-around gate CNTFETs, also known
as gate-all-around CNTFETs were
developed in 2008,[20] and are a further
improvement upon the top-gate device
geometry. In this device, instead of gating
just the part of the CNT that is closer to
the metal gate contact, the entire
circumference of the nanotube is gated.
Sheathed CNT
Gate all-around CNT Device

This should ideally improve the electrical
performance of the CNTFET, reducing
leakage current and improving the device
on/off ratio.
Device fabrication begins by first wrapping
CNTs in a gate dielectric and gate contact
via atomic layer deposition.[21] These
wrapped nanotubes are then solution-
deposited on an insulating substrate,
where the wrappings are partially etched
off, exposing the ends of the nanotube.
The source, drain, and gate contacts are
then deposited onto the CNT ends and the
metallic outer gate wrapping.

Suspended CNTFETs
Yet another CNTFET device geometry
involves suspending the nanotube over a
trench to reduce contact with the
substrate and gate oxide.[22] This
technique has the advantage of reduced
scattering at the CNT-substrate interface,
improving device performance.[22][23][24]
There are many methods used to fabricate
A suspended CNTFET device.

suspended CNTFETs, ranging from
growing them over trenches using catalyst
particles,[22] transferring them onto a
substrate and then under-etching the
dielectric beneath,[24] and transfer-printing
onto a trenched substrate.[23]
The main problem suffered by suspended
CNTFETs is that they have very limited
material options for use as a gate
dielectric (generally air or vacuum), and
applying a gate bias has the effect of
pulling the nanotube closer to the gate,
which places an upper limit on how much
the nanotube can be gated. This technique
will also only work for shorter nanotubes,

as longer tubes will flex in the middle and
droop towards the gate, possibly touching
the metal contact and shorting the device.
In general, suspended CNTFETs are not
practical for commercial applications, but
they can be useful for studying the
intrinsic properties of clean nanotubes.
CNTFET material considerations
There are general decisions one must
make when considering what materials to
use when fabricating a CNTFET.
Semiconducting single-walled carbon
nanotubes are preferred over metallic
single-walled and metallic multi-walled

tubes since they are able to be fully
switched off, at least for low source/drain
biases. A lot of work has been put into
finding a suitable contact material for
semiconducting CNTs; the best material to
date is Palladium, because its work
function closely matches that of
nanotubes and it adheres to the CNTs
quite well.[25]

In CNT–metal contacts, the different work
functions of the metal and the CNT result
in a Schottky barrier at the source and
drain, which are made of metals like silver,
titanium, palladium and aluminum.[27] Even
though like Schottky barrier diodes, the
I–V characteristics
Field effect mobility of a back-gated CNTFET device with varying channel lengths. SiO2 is used as the gate dielectric. Tool:
'CNT Mobility' at nanoHUB.org[26]

barriers would have made this FET to
transport only one type of carrier, the
carrier transport through the metal-CNT
interface is dominated by quantum
mechanical tunneling through the Schottky
barrier. CNTFETs can easily be thinned by
the gate field such that tunneling through
them results in a substantial current
contribution. CNTFETs are ambipolar;
either electrons or holes, or both electrons
and holes can be injected
simultaneously.[27] This makes the
thickness of the Schottky barrier a critical
factor.

CNTFETs conduct electrons when a
positive bias is applied to the gate and
holes when a negative bias is applied, and
drain current increases with increasing a
magnitude of an applied gate voltage.[28]
Around Vg = Vds/2, the current gets the
minimum due to the same amount of the
electron and hole contributions to the
current.
Like other FETs, the drain current
increases with an increasing drain bias
unless the applied gate voltage is below
the threshold voltage. For planar CNTFETs
with different design parameters, the FET
with a shorter channel length produces a

higher saturation current, and the
saturation drain current also becomes
higher for the FET consisting of smaller
diameter keeping the length constant. For
cylindrical CNTFETs, it is clear that a
higher drain current is driven than that of
planar CNTFETs since a CNT is
surrounded by an oxide layer which is
finally surrounded by a metal contact
serving as the gate terminal.[29]
Theoretical derivation of drain current

Theoretical investigation on drain current
of the top-gate CNT transistor has been
done by Kazierski and colleagues.[30]
When an electric field is applied to a CNT
transistor, a mobile charge is induced in
the tube from the source and drain. These
charges are from the density of positive
velocity states filled by the source NS and
that of negative velocity states filled by the
drain ND,[30] and these densities are
determined by the Fermi–Dirac probability
distributions.
Structure of a top-gate CNT transistor

and the equilibrium electron density is
.
where the density of states at the channel
D(E), USF, and UDF are defined as

The term, is 1 when the
value inside the bracket is positive and 0
when negative. VSC is the self-consistent
voltage that illustrates that the CNT energy
is affected by external terminal voltages
and is implicitly related to the device
terminal voltages and charges at terminal
capacitances by the following nonlinear
equation:
where Qt represents the charge stored in
terminal capacitances, and the total

terminal capacitance CΣ is the sum of the
gate, drain, source, and substrate
capacitances shown in the figure above.
The standard approach to the solution to
the self-consistent voltage equation is to
use the Newton–Raphson iterative
method. According to the CNT ballistic
transport theory, the drain current caused
by the transport of the nonequilibrium
charge across the nanotube can be
calculated using the Fermi–Dirac
statistics.

Here F0 represents the Fermi–Dirac
integral of order 0, k is the Boltzmann
constant, T is the temperature, and ℏ the
reduced Planck constant. This equation
can be solved easily as long as the self-
consistent voltage is known. However the
calculation could be time-consuming when
it needs to solve the self-consistent
voltage with the iterative method, and this
is the main drawback of this calculation.
Better control over channel formation
Better threshold voltage
Better subthreshold slope
Key advantages

High electron mobility
High current density
High transconductance
High linearity
CNTFETs show different characteristics
compared to MOSFETs in their
performances. In a planar gate structure,
the p-CNTFET produces ~1500 A/m of the
on-current per unit width at a gate
overdrive of 0.6 V while p-MOSFET
produces ~500 A/m at the same gate
voltage.[31] This on-current advantage
comes from the high gate capacitance and
Comparison to MOSFETs

improved channel transport. Since an
effective gate capacitance per unit width
of CNTFET is about double that of p-
MOSFET, the compatibility with high-k gate
dielectrics becomes a definite advantage
for CNTFETs.[29] About twice higher carrier
velocity of CNTFETs than MOSFETs
comes from the increased mobility and the
band structure. CNTFETs, in addition, have
about four times higher transconductance.
The first sub-10-nanometer CNT transistor
was made which outperformed the best
competing silicon devices with more than
four times the diameter-normalized
current density (2.41 mA/μm) at an

operating voltage of 0.5 V. The inverse
subthreshold slope of the CNTFET was 94
mV/decade.[32]
The decrease of the current and burning of
the CNT can occur due to the temperature
raised by several hundreds of kelvins.
Generally, the self-heating effect is much
less severe in a semiconducting CNTFET
than in a metallic one due to different heat
dissipation mechanisms. A small fraction
of the heat generated in the CNTFET is
dissipated through the channel. The heat
is non-uniformly distributed, and the
highest values appear at the source and
Heat dissipation

drain sides of the channel.[33] Therefore,
the temperature significantly gets lowered
near the source and drain regions. For
semiconducting CNT, the temperature rise
has a relatively small effect on the I–V
characteristics compared to silicon.
Lifetime (degradation)
Carbon nanotubes have recently been
shown to be stable in air for many months
and likely more, even when under continual
operation.[34] While gate voltages are
being applied, the device current can
experience some undesirable drift/settling,
Disadvantages

but changes in gating quickly reset this
behavior with little change in threshold
voltage.[34]
Reliability
Carbon nanotubes have shown reliability
issues when operated under high electric
field or temperature gradients. Avalanche
breakdown occurs in semiconducting CNT
and joule breakdown in metallic CNT.
Unlike avalanche behavior in silicon,
avalanche in CNTs is negligibly
temperature-dependent. Applying high
voltages beyond avalanche point results in
Joule heating and eventual breakdown in

CNTs.[35] This reliability issue has been
studied, and it is noticed that the multi-
channeled structure can improve the
reliability of the CNTFET. The multi-
channeled CNTFETs can keep a stable
performance after several months, while
the single-channeled CNTFETs usually
wear out after a few weeks in the ambient
atmosphere.[36] The multi-channeled
CNTFETs keep operating when some
channels break down, with a small change
in electrical properties.

Difficulties in mass production,
production cost
Although CNTs have unique properties
such as stiffness, strength, and tenacity
compared to other materials especially to
silicon, there is currently no technology for
their mass production and high production
cost. To overcome the fabrication
difficulties, several methods have been
studied such as direct growth, solution
dropping, and various transfer printing
techniques.[37] The most promising
methods for mass production involve
some degree of self-assembly of pre-
produced nanotubes into the desired

positions. Individually manipulating many
tubes is impractical at a large scale and
growing them in their final positions
presents many challenges.
The most desirable future work involved in
CNTFETs will be the transistor with higher
reliability, cheap production cost, or the
one with more enhanced performances.
For example: adding effects external to the
inner CNT transistor like the Schottky
barrier between the CNT and metal
contacts, multiple CNTs at a single
gate,[30] channel fringe capacitances,
parasitic source/drain resistance, and
Future work

series resistance due to the scattering
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