1. Niraja Paranjape
1701, E 8th Street, apt 105 Tempe, AZ 85281
Phone: 4803329872 E-Mail: nirajaparanjape@gmail.com
Education
Arizona State University, Tempe, Arizona Aug 2014 – May 2016
Master of Science, Electrical Engineering (GPA 3.61/4)
Birla Institute of Technology and Science Aug 2007 – Jul 2012
Master of Science (Hons.), Physics
Bachelor of Engineering (Hons.), Electronics and Instrumentation
Experience
Teaching Assistant, Arizona State University Aug 2015 - Present
! Assisting students with laboratory projects for Advanced Analog Integrated Circuits. Includes testing and
verifying the lab projects
AMS Verification and GLS Engineer, Qualcomm India Pvt. Ltd. Jul 2012 – Jun 2014
! Analog/Mixed-signal Verification of PLL, ADC, DAC with Gate-level and timing simulations for 28nm and
20nm processes and support for post-silicon debug
! System Verilog simulation and vector generation for testing the above blocks
! Creating a test plan for PLL and ADC verification
! Appreciation award for successful execution in 3 projects.
Academic Projects
Design of a Voltage-Controlled Oscillator using IBM7RF process April 2015
Design and Layout of a CMOS based differential VCO for a frequency of 2.4 GHz
Circuit Design of RF Transceiver components using IBM7RF process Feb-Mar 2015
! Inductively Degenerated Common-Source Low Noise Amplifier at a frequency of 2.4 GHz
! Gilbert-cell Mixer for an RF frequency of 2.41 GHz and an LO frequency of 2.4 GHz
Design of a 1.6GHz Phase Locked Loop (PLL) using TSMC 180nm PDK Sep-Nov 2014
Transistor level design of a PLL for a frequency of 1.6 GHz using a reference clock of 100 MHz
Power Amplifier Design using ADS Sep-Nov 2015
! Class A, B and C PAs were designed at 1 GHz
! Class F PA designed at 940 MHz using a 50-V NXP (Freescale) LDMOS model
! A Fully symmetrical Doherty Amplifier was designed for a frequency of 1GHz
Design and layout of a 1.5A Low Drop-Out voltage regulator Feb-Apr 2015
An ultra low-noise, high-PSRR LDO was designed for a fixed output voltage of 1.5V using TSMC 180nm process.
Modeling of a Simultaneous Transmit and Receive (STAR) Transceiver Oct-Nov 2015
A MATLAB model of a STAR transceiver was designed to measure the Self-Interference from the transmitted
signal. A Built-in Self Test circuit is used to measure the reflected signal.
Operational Amplifier and OTA design using TSMC 250nm process Feb-Apr 2015
Design of Op Amp and OTA using a Beta-Multiplier as a reference
Tape-out May 2015
Taped out a Ramp-generator and Operational Amplifier as a part of a group project. The process, AMS 180nm
HV CMOS, was used.
Skills and Courses
RF Power Amplifiers, Communication Transceiver Circuit Design, Microwave Circuit Design, Advanced
Analog Integrated Circuits, Digital Systems and Circuits
EDA Tools: Cadence, ModelSim
Softwares: ADS, MATLAB, and Simulink
Programming Languages: C/C++, PERL, Verilog HDL, System Verilog