1. Xiaoyi Huang
10629 Exeter Ave NE, Seattle, WA 98125 • 213-392-9879 • xiaoyihuang92@gmail.com
OBJECTIVE
To obtain a full time position as an Integrated Circuit Designer specializing in Analog Electronics. Available
Now.
EDUCATION
Case Western Reserve University Cleveland, OH
Bachelor of Science, Electrical Engineering Graduated May 2015
EXPERIENCE
Case Western Reserve University, Cleveland, OH January – May 2015
Group Project: Superheterodyne AM Radio Receiver Design
 Designed a superheterodyne AM radio receiver which can receive carrier waves with radio frequency
locating in 535kHz to 1700kHz using NI Multisim. Built the receiver powered by a 3V battery and
soldered circuits on a PCB board.
 Applied BJT frequency multiplier technique to design a Mixer to mix the incoming RF signal and local
oscillator signal then down convert the carrier signal to IF signal at 455kHz.
 Designed an IF amplifier with AGC circuit controlled by DC component in envelope detector output to
amplify IF signal and suppress noise.
Case Western Reserve University, Cleveland, OH August – December 2014
Group Project: Adaptive Noise Cancelling Headset Specializing in Cancelling Low Frequency Noise
 Designed an adaptive noise canceller for noise in 50 to 500Hz based on OMAP-L138 LCDK DSP board.
 Explored Least Mean Square algorithm and implemented its modified algorithm Normalized LMS by C on
CCS. Adopted 8kHz sampling frequency and 64-order filter to increase converging speed.
 Designed and soldered a collector circuit with a -35dB omnidirectional microphone, a -35dB cardioid
microphone and two coupling capacitors to collect reference noise and error signal and an adder circuit
based on op-amp to control the gain and mix the noise and anti-noise signal.
 Achieved a canceller with an average noise reduction factor of 21dB between 150Hz and 500Hz, which has
an average noise reduction factor of 13dB in real-word road side noise test.
Case Western Reserve University, Cleveland, OH August – December 2014
Software 4-QAM Receiver Design in Digital Communication System
 Designed a radio receiver with adaptive layer for carrier recovery, timing recovery, equalizer adaptation
and frame synchronization on MATLAB which can tolerate 1% intersymbol interference (ISI).
 Designed a demodulator containing a mixer followed by an FIR lowpass filter and designed a carrier
recovery with approaches of PLL and Costas Loop.
 Designed a timing recovery using the iterative cluster variance algorithm to choose an instant at which to
sample incoming analog signal. Designed a linear equalizer based on LMS to surmount ISI.
 Designed a frame synchronization approaching by peakiness of the correlation of the marker.
Case Western Reserve University, Cleveland, OH March – April 2014
LC Tank Voltage Controlled Oscillator Design
 Designed an oscillator outputting 1V sinusoid in 15MHz to 35MHz with active power higher than 20mW.
 Explored Colpitts oscillator and used it as foundation of VCO design. Implemented voltage controlling by
replacing the capacitor in parallel LC circuit with a veractor.
 Designed a two-stage amplifier: voltage amplifier stage using frequency selective amplifier resonating at
30MHz and power output stage using class E power amplifier.
SKILLS
Software: MATLAB, NI Multisim, OrCAD Capture CIS, Modelsim, Microsoft Office
Hardware: Filter Design, Amplifier Design, Oscillator, PLL, DSP board
Knowledge: Java, Digital Signal Processing, Modulation, Solid-state Device, Data Structure