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Devdutt Pawaskar Resume


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Devdutt Pawaskar Resume

  1. 1. 144 Ponce de Leon Avenue DEVDUTT PAWASKAR +1 (470) 985-3044 Atlanta, GA 30308 Objective Graduate student seeking full-time opportunities starting Dec 2016 in VLSI Systems Design. Education Georgia Institute of Technology, Atlanta, GA GPA: 3.55 Aug ’15 - Dec ’16 Master of Science, Electrical and Computer Engineering Specialization: VLSI Systmes and Digital Design Coursework: Advanced VLSI Systems, High Performance Computer Architecture, Digital Systems Testing, Physical Design Automation – VLSI, Computer Aided VLSI System Design, Parallel and Distributed Computer Architecture Maharaja Sayajirao University, India GPA: 3.99 ’08 – ’12 Bachelors of Engineering, Electronics Engineering Skills Programming Languages: C++, Assembly Level Programming (8051), Verilog Scripting Languages: PERL Circuit Tools: Synopsys (Design Vision, Design Compiler, Primeime, VCS, Waveview), Cadence (Virtuoso, Encounter, ADE, SPECTRE), ModelSim, QRC Extraction tools, HSPICE Circuit Design Concepts: Bit-cell analysis, SRAM, DRAM, Fully Integrated Voltage Regulator (FIVR), RTL design and synthesis, parasitic extraction, Sense amplifier, physical design automation algorithms, clocking, power delivery and dissipation Software: MATLAB, Keil, Eagle, COMOS, CONVAL, Teamcenter (Siemens PLM Software) Experience Siemens Ltd., Vadodara, India July ’12 – July ’15 Executive Engineer • Constructed P&IDs, logic diagrams, wiring diagrams, instrument specifications for compressor package in COMOS • Designed and appropriately sized the Anti-Surge control valve in CONVAL within limited time and instructions Projects Implementation of digital compensator for a Fully Integrated Voltage Regulator (FIVR) with dynamic precision and operating frequency in 130nm library Aug ’16 - Present • Synthesis and timing closure of the design in 130nm library • Placement and routing using Encounter including placement of antenna diodes, decoupling capacitor cells and power grid • Retiming/ECO using primetime and Encounter • DRC and LVS clearance of top level including chip pads Design of Compensator for very high frequency Inductive Fully Integrated Voltage Regulator (FIVR) in 28nm May ’16 - Aug ’16 Understood design space between data precision and operating frequency of a digital compensator for FIVR. Increasing operating frequency improves loop bandwidth and FIVR response to power transitions. • Developed PERL script to generate Verilog files based on variable inputs • Designed and synthesized RTLs for different compensator structures (direct form FIR filters), and functionally verified them through testbenches via gate-level simulations in ModelSim and Synopsys VCS • Performed critical path analysis of gate-level netlists using their sdf files to characterize maximum operating frequencies for different compensator configurations • Performed post-synthesis power estimation using Primetime Design and Implementation of 45nm 6-T SRAM and Arithmetic Unit Aug ’15 - Dec ’15 • Implemented a pipelined system of 64 byte 6-T SRAM array, to drive a 150nF interconnect and CLA Adder • Designed row and column decoders and WordLine (WL) generation block using low VT MOSFETs • Performed bit-cell analysis to achieve optimum β – ratios for the 6-T cell, so as to maintain read and write margins within specified limits • Created layouts for bitcell, WL driver, BL pre-charge and column multiplexer, and integrated it in the schematic Noise tolerant Low Power Dynamic NOR gate in 45nm technology Oct ’15 • Designed a 32 input Dynamic NOR gate having precharge and worst case high to low delays of 146.5ps and 46.3ps respectively • Noise margin was improved from 88mV to 248mV by introducing a keeper and increasing its size from 100nm to 400nm Implementation of Circuit simulator, Fault simulator and PODEM (ATPG) algorithm Sep ’15 - Dec ’15 • Developed a Logical Circuit simulator to read and construct gate level circuit from a file • Implemented Deductive Fault Simulator (C++) • Upgraded the same to an ATPG algorithm, PODEM (Path Oriented Decision Making) to generate test vectors for stuck-at faults in the circuit. The test vectors were verified using the previously designed deductive fault simulator (C++)