The document describes the design of a voltage-controlled oscillator (VCO) in Cadence. First, the inductor and transistors were analyzed separately to determine specifications. A schematic was designed meeting the desired phase noise performance and optimized for lower power. Simulation results showed the VCO tuning range of 890-930MHz and phase noise between -149 to -159dBc at 1MHz offset for various frequencies. Post-layout simulations matched the pre-layout results with 4.3mW power and 0.1362mm2 area.

1. EECS 522
CAD#3
Nagarjun Bhat
UMID: 76047405
Design:
First, the symmetric inductor was analyzed in Cadence separately to find its peak quality factor and from that the
parasitic series resistance Rs was calculated. From the formula in handout, the equivalent parallel resistance was
obtained and gm of the transistors decided on this basis to obtain oscillation.
At the same time, setting an Ibias of 3mA, and using the given spec of Vpp needed, Rp was obtained. And once again the
gm of the transistors extracted. The best of these values which gave the desired Phase noise performance was chosen
for final design.
The design was later optimized for lower power consumption, w9ith changes in biasing voltages.
Shown below is the schematic of the design:
Figure 1: Schematic of the designed VCO
Passives used: Symmetric Inductor, Dualmimcap-1 nos and Ncap (as varactor)-2Nos.
The PSS and Pnoise analyses were run on the schematic and then layout and a good conformation was obtained.

2. EECS 522
CAD#3
Nagarjun Bhat
UMID: 76047405
The Table below summarizes the values of devices used in the design
Name/Device Dimensions Value
T3/ NFET_RF W=30u, L=130n, Nf=10 Region:2 Id=3.68mA
T5/ NFET_RF W=30u, L=130n, Nf=10 Region:2 Id=3.68mA
T4/ NFET_RF W=30u, L=130n, Nf=10 Region:2 Id=3.68mA
Symindp/Symmetric Stacked Inductor with Centre Tap W=285u,L=8.5u, N=5 L=6.78nH
CM13/DualmimCap W=32.03u, L=18u Cap=3.3pF
CN0 W=16u, L=9u Cap=1.5pF
CN2 W=16u, L=9u Cap=1.5pF
Table 1: Specifications of all devices used
Shown below are the results obtqained from simulation of the schematic.
Figure 2: Schematic tuning range

3. EECS 522
CAD#3
Nagarjun Bhat
UMID: 76047405
Figure 3: Oscillation amp@915MHz_ schematic (Vpp=5Vpp) and Phase noise from schematic
Figure 4: Phase_Noise_902MHz and 928MHz(right)

4. EECS 522
CAD#3
Nagarjun Bhat
UMID: 76047405
Layout
Figure 5: Layout of VCO, zoomed on the right
The layout is both DRC and LVS clean!
Figure 6: DRC Clean

5. EECS 522
CAD#3
Nagarjun Bhat
UMID: 76047405
Figure 7: LVS Clean
POST PEX RESULTS:
The following table summarizes all the specifications and performance of the designed VCO
Power Consumed Post PEX: 4.3mW
Area: 0406mm X 0.335mm=0.1362mm2
Vbias1=800m
Vbias2=NA
Vtune:0-1.2V
Specification Pre-PEX Post-PEX
Tuning Range 900MHz-928MHz 890MHz-930MHz
Phase Noise -160dBc @1MHz offset for f0=902MHz
-156dBc @1MHz offset for f0=915MHz
-149dBc @1MHz offset for f0=928MHz
-158dBc @1MHz offset for f0=902MHz
-159dBc @1MHz offset for f0=915MHz
-150dBc @1MHz offset for f0=928MHz
Differential Op 3.4Vpp 2.82Vpp,3Vpp,3.1Vpp

6. EECS 522
CAD#3
Nagarjun Bhat
UMID: 76047405
Figure 8: Post PEX_Tuning range and Phase noise for all frequencies Post PEX
Figure 9: Post PEX Phase Noise,@f0=902MHz and 2.818Vpp for 902MHz_Post PEX

7. EECS 522
CAD#3
Nagarjun Bhat
UMID: 76047405
Figure 10: Phase Noise_915MHz_schematic and Vpp=3.16V for @f0=915MHz, Post PEX
Figure 11: Phase noise @f0=928MHz, post PEX and Vpp=3.1V @ 928MHz, post PEX