This document discusses digital signal processors and their architecture. It describes the architecture of TMS320C5x digital signal processors, including their bus structure, central processing unit components like the central arithmetic logic unit and parallel logic unit, on-chip memory, and applications like speech processing and biomedical signal processing. Key features of the TMS320C5x like separate program and data buses, memory-mapped registers, and dual access RAM are summarized.
2. UNIT V DIGITAL SIGNAL PROCESSORS
๏ DSP memory architecture - Architecture and features
of TMS320C5X, Instruction set, Addressing modes
Architecture and features of TMS320C54X - DSP
applications in biomedical signal processing - Voice
processing, RADAR.
9. Bus structure
๏ Separate program and data buses allow simultaneous access
to program instructions and data, providing a high degree of
parallelism.
๏ Such parallelism supports a powerful set of arithmetic, logic,
and bit-manipulation operations that all can be performed in a
single machine cycle. In addition, the 'C5xincludes the control
mechanisms to manage interrupts, repeated operations, and
function calling.
๏ The 'C5x architecture is built around four major buses:
Program bus (PB) Program address bus (PAB) Data read bus
(DB) Data read address bus (DAB)
๏ The PAB provides addresses to program memory space for
both reads and writes.
๏ The PB also carries the instruction code and immediate
operands from program memory space to the CPU. The DB
interconnects various elements of the CPU to data memory
space.
10. Central Processing Unit (CPU)
๏ The 'C5x CPU consists of these elements: Central
arithmetic logic unit (CALU) Parallel logic unit (PLU)
Auxiliary register arithmetic unit (ARAU) Memory-
mapped registers Program controller.
๏ The 'C5x CPU maintains source-code compatibility with
the 'Clx and "C2x generations while achieving high
performance and greater versatility. Improvements
include a 32-bit accumulator buffer, additional scaling
capabilities, and a host of new instructions.
๏ The instruction set exploits the additional hardware
features and is flexible in a wide range of applications.
Data management has been improved through the use
of new block move instructions and memory-mapped
register instructions.
11. Central Arithmetic Logic Unit
(CALU)
๏ The CPU uses the CALU to perform 2s-complement
arithmetic. The CALU consists of these elements: 16-bit
multiplier 32-bit arithmetic logic unit (ALU) 32-bit
accumulator (ACC) 32-bit accumulator buffer(ACCB)
Additional shifters at the outputs of both the
accumulator and the product register (PREG)
12. Parallel Logic Unit (PLU)
๏ The CPU includes an independent PLU, which
operates separately from, but in parallel with, the ALU.
The PLU performs Boolean operations or the bit
manipulations required of high-speed controllers.
๏ The PLU can set, clear, test, or toggle bits in a status
register, control register, or any data memory location.
๏ The PLU provides a direct logic operation path to data
memory values without affecting the contents of the
ACC or PREG. Results of a PLU function are written
back to the original data memory location
13. Auxiliary Register Arithmetic Unit (ARAU)
๏ The CPU includes an unsigned 16-bit arithmetic logic
unit that calculates indirect addresses by using inputs
from the auxiliary registers (ARS), index register
(INDX), and auxiliary register compare register (ARCR).
๏ The ARAU can auto index the current AR while the
data memory location is being addressed and can
index either by 1 or by the contents of the INDX. As a
result, accessing data does not require the CALU for
address manipulation; therefore, the CALU is free for
other operations in parallel.
14. Memory-Mapped Registers
๏ The 'C5x has 96 registers mapped into page 0 of the data memory
space. All 'C5x DSPs have 28 CPU registers and 16 input/output
(I/O) port registers but have different numbers of peripheral and
reserved registers.
๏ Since the memory-mapped registers are a component of the data
memory space, they can be written to and read from in the same
way as any other data memory location.
๏ The memory-mapped registers are used for indirect data address
pointers, temporary storage, CPU status and control, or integer
arithmetic processing through the ARAU.
The program controller contains logic circuitry that decodes the
operational instructions, manages the CPU pipeline, stores the
status of CPU operations, and decodes the conditional operations.
๏ Parallelism of architecture lets the 'C5x perform three concurrent
memory operations in any given machine cycle: fetch an instruction,
read an operand, and write an operand. Program counter Status and
control registers Hardware stack Address generation logic Instruction
register.
15. On-Chip Memory
๏ The 'C5x architecture contains a considerable amount of on-chip memory to aid
in system performance and integration: Program read-only memory (ROM) Data
/ program dual-access RAM (DARAM) Data/program single-access RAM
(SARAM)
๏ The 'C5x has a total address range of 224K words 16 bits. The memory space
is divided into four individually selectable memory segments: 64K-word program
memory space, 64K-word local data memory space, 64K-word input/ output
ports, and 32K-word global data memory space.
๏ For information on the memory organization, Program ROM All 'C5x DSPs carry
a 16-bit on-chip maskable programmable ROM. The "C50 and 'C57S DSPs
have boot loader code resident in the on-chip ROM, all other C5x DSPs offer the
boot loader code as an option.
๏ This memory is used for booting program code from slower external ROM or
EPROM to fast on-chip or external RAM. Once the custom program has been
booted into RAM, the boot ROM space can be removed from program memory
space by setting the MP/MC bit in the processor mode status register (PMST).
๏ The on-chip ROM is selected at reset by driving the MP/MC pin low. If the on-
chip ROM is not selected, the 'C5x devices start execution from off-chip memory.
For information on the program ROM, Program Memory.
๏ The on-chip ROM may be configured with or without boot loader code.
However, the on-chip ROM is intended for your specific program. Once the
program is in its final form, you can submit the ROM code to Texas Instruments
for implementation into your device.
16. Data/Program Single-Access RAM
๏ All SARAM configured as data memory All SARAM configured as
program memory SARAM configured as both data memory and program
memory The SARAM is
divided into 1K- and/or 2K-word blocks contiguous in address memory
space. All
'C5x CPUs support parallel accesses to these SARAM blocks.
๏ However, one SARAM block can be accessed only once per machine
cycle. In other
words, the CPU can read from or write to one SARAM block while
accessing another
SARAM block.
๏ When the CPU requests multiple accesses, the SARAM schedules the
accesses by
providing a not-ready condition to the CPU and executing the multiple
accesses one
cycle at a time.
๏ SARAM supports more flexible address mapping than DARAM because
SARAM
can be mapped to both program and data memory space
simultaneously.
๏ However, because of simultaneous program and data mapping, an
19. Applications of DSP in Bio-Medical Engineering
โ Fetal ECG Monitoring
โขThe fetal electro cardiogram (ECG) shows the electrical activity of the
baby's heart as measured from the body surface.
โขCardiotocogram (CTG), is normally used to access the condition of the
fetus during labor. But, it leads to unnecessary medical intervention, fetal
injury or a failure to intervene when needed. This is overcome by the
correct use of combined fetal ECG and CTG analysis, with no adverse
effect on neonatal outcome.
โข First the R-wave is accurately detected. The baseline shift, muscle noise
and power line frequencies are then removed from the raw ECG to obtain
a waveform suitable for reliable analysis.
20. ๏ The ECG is obtained from a scalp electrode to achieve
a good signal-to-noise ratio, band limited to about 0.05-
100Hz and digitized to 12 bits accuracy at a rate of 500
samples per second.
๏ The fetal scalp ECG is susceptible to low frequency
noise and other artefacts which may induce false
changes in the waveform. Artefacts hinder features
extraction may lead to inaccurate ECG features and
waveform analysis.
๏ A variety of signal processing methods are used to
reduce noise and extract key features from the ECG. A
fetal ECG signal processing
22. ๏ Patients are normally anaesthetized during surgery by
injecting anesthetic drugs, so that they do not feel pain and
to create a suitable condition for the surgeon to carry out the
operation.
๏ To deliver proper amount of drug to induce anaesthesia at
required depth as quickly as possible and to maintain the
level is most important.
๏ Injecting too much drug into a patient leads to side effect
while less amount of drug leads to intra-operative
awareness which may have long term psychological
consequences.
๏ Automated drug delivery using closed loop control
techniques offers potential benefits to busy anesthetists and
leads to better patient care at lower costs.
๏ Its use reduces the possibility of excessive dosing and
enables the anesthetist to identify and respond. However,
automated closed loop controlled drug delivery required a
reliable means of monitoring depth of anesthesia to
determine changes to the drug delivery necessary to
maintain anesthesia.
๏ Closed-controlled anesthesia systems use biological signals
23. DSP -based Closed Loop Controlled
Anaesthesia
EEG analyzer is the major component which is connected to the patient
through bifrontal electrodes to collect raw EEG signals. A variety of
signal processing methods are used in the analyzer to reduce noise,
extract features, analyze changes in the features, and to compute a
suitable EEG index. These include wavelet transform, signal averaging,
bispectrum analysis and neutral networks.
24. Speech Processing
๏ The speech signal is a slowly time varying signal. The
speech signal can be broadly classified into voiced and
unvoiced signal. The voiced signals are periodic in nature
and unvoiced signals are random in nature.
๏ For representing a characteristic sound of the speech the
voiced signals will have a fundamental frequency in a
segment of 15 to 20 msec. The various frequency
components of sounds in speech signal lies within 4 kHz.
The DSP based speech processing techniques can be
classified into two broad categories viz., speech analysis
and speech synthesis.
๏ Speech analysis: In general, the process of extracting the
features of speech, then coding or directly digitalizing the
speech and then reducing the bit rate is called speech
analysis.
25. Speech Coding and Decoding
๏ The speech coding is digital representation of speech
using minimum bit rate without affecting the voice
quality.
๏ The speech decoding is the conversion of digital
speech data to analog speech.
๏ The old method for quality transmission and reception
of digital speech signal through telephone lines,
employs a bit rate of 64 kbps (kilo bits per second).
This digital representation is called Pulse Code
Modulation (PCM) in which the speech signal is
sampled at 8 kHz and each sample is quantized to 13
bits and then compressed to 8 bits using ฮผ law or A-law
standards to achieve a transmission rate of 64 kbps
(8000 samples per second x8 bits per sample = 64000
26. Speech Coding and Decoding
๏ For effective utilization the transmission channels and to reduce
memory requirements for storage and retrieval of speech, a
number of digital speech coding techniques are developed to
represent the speech at lower bit rates up to 1000 bits per
second. The speech coding techniques can be broadly classified
into waveform coding techniques and parametric coding
techniques.
๏ Some of the popular waveform coding techniques employed are
Adaptive Pulse Code Modulation (APCM), Differential Pulse Code
Modulation (DPCM) and Adaptive Differential Pulse Code
Modulation (ADPCM).
๏ Some of the parametric methods of speech coding are Linear
Prediction Coding (LPC), Mel-Frequency Cepstrum Coefficients
(MFCC), Code Excited Linear Prediction Coding (CELP) and
Vector Sum Excited Linear Prediction (VSELP).
27. Adaptive Differential Pulse Code Modulation
(ADPCM)
๏ The DPCM (Differential Pulse Code Modulation)
method of speech analysis/coding is based on the
assumption that a speech sample can be effectively
represented by the difference between previous and
current sample.
๏ In the ADPCM method, the difference signal is
computed between an adaptively predicted sample and
current sample. Since, the difference between two
samples can be represented by fewer bits, a 2:1
compression can be achieved, so that a 64 kbps
speech signal can be coded to 32 kbps signal.
28. Adaptive Differential Pulse Code Modulation
(ADPCM)
The analog speech signal is converted into 64kbps digital speech signal
by sampling at 8 kHz with 8-bit per sample using an audio codec.
The ADPCM algorithm expand this 8-bit samples to 14-bit samples and
subtract each expanded sample with an adaptively predicted sample to
generate a difference signal which is quantized to 4 bits.
The output of the quantizer is the coded speech signal. The adaptively
predicted signal is a weighted average of some dequantized difference
signals and some predicted samples.
29. The ADPCM algorithm employs an inverse quantizer to generate the
dequantized difference signal, from the coded speech sample.
The ADPCM algorithm reconstructs the 14-bit sample of speech by adding
the dequantized difference signal and an adaptively predicted signal
estimate. Then the 14-bit speech samples are converted to 8-bit samples,
which represents the decoded speech.
The decoded speech can be converted to analog speech using an audio
codec.
30. ๏ The ADPCM algorithm employs an inverse quantizer
to generate the dequantized difference signal, from
the coded speech sample.
๏ The ADPCM algorithm reconstructs the 14-bit sample
of speech by adding the dequantized difference signal
and an adaptively predicted signal estimate. Then the
14-bit speech samples are converted to 8-bit
samples, which represents the decoded speech.
๏ The decoded speech can be converted to analog
speech using an audio codec.
31. Linear Predictive Coding (LPC)
๏ The LPC method of speech analysis/coding is based on the
assumption that a speech sample can be approximated as a
linear combination of previous speech samples. In LPC
coding method bit rates up to 24000 bits per second can be
achieved.
๏ For speech coding, first the speech signal is digitalized
using a coding system, in which the speech signal is
segmented to 20 msec, sampled at 8 to 12 kHz. Then a set
of filter coefficients are determined by using these samples.
๏ A pitch is also calculated for each voiced speech segment.
The filter coefficients and the pitch represent the coded
speech.
๏ In the decoding process, a digital filter is constructed using
the filter coefficients, with input as a train of impulses at the
pitch frequency for voiced segments and random noise
sequence for unvoiced segments. The output of this filter is
32. Mel-Frequency Cepstrum Coefficients (MFCC)
๏ MFCC method of speech coding/analysis is based on the knowledge of
variation of human ear's critical bandwidths with frequency. In this
method, the phonetically important characteristics of speech are
obtained using filters. The lower frequencies are expressed in linear
frequency scale and high frequencies by logarithmic scale and these
characteristics are expressed in Mel-frequency scale.
๏ The input 64 kbps speech data are converted to frames representing 20
msec of speech. Each frame data is overlapped by 5 msec on either
side with adjacent frame and then windowed using hamming window to
minimize the effects of signal discontinuity at the beginning and end of
each frame. Then FFT is computed to determine the frequency
spectrum of the frame.
33. For each tone frequency in the spectrum, a mel-spectrum coefficient is
assigned using mel-scale. This process is called mel-frequency wrapping.
The mel-spectrum coefficients are converted into time domain coefficients
called MFCC using discrete cosine transform. Thus each overlapped 30
msec speech frame is coded into a set of Mel-Frequency Cepstrum
Coefficients (MFCC). This set of coefficients is also called an acoustic
vector.
34. Vector Sum Excited Linear Prediction
(VSELP)
๏ Vector Sum Excited Linear Prediction method of
speech coding technique compresses the 64 kbps
digital speech signal to 6.95 kbps code.
๏ The 64 kbps speech data are converted to frames at a
rate of 50 frames per second, so that each frame
represent 20 msec speech and will consist of 160
samples. Then each frame is coded into 159 bits using
code book search techniques.
35. Speech Recognition
โขA speech recognition system can function in many different
conditions such as speaker-independent/dependent and
isolated/continuous speech recognition.
โขA speaker-dependent system recognizes a specific speaker's
speech, while the speech of any unspecified speaker is recognized
by using speaker-independent systems.
โขIn an isolated word recognition system, each word or a simple
utterance is assumed to be surrounded by silence or background
noise. Connected speech or connected utterance recognition is
similar to isolated word recognition. But it allows several words
/digits to be spoken together with a minimum pause between them.
36. Speech Recognition
๏ The front end analysis extracts the acoustic features of input
speech. Some of the popular techniques used for extracting the
acoustic features of speech are Linear Prediction Coding (LPC),
Mel-Frequency Cepstrum Coefficients (MFCC) and Perceptual
Linear Prediction (PLP).
๏ The output of front-end analysis is a compact, efficient set of
parameters that represent the acoustic properties observed from
input speech signals, for subsequent utilization by acoustic
modeling.
๏ The acoustic models represent the acoustic properties, phonetic
properties, microphone and environmental viability, as well as
gender and dialectal differences among speakers.
๏ The language models contain the syntax, semantics and
pragmatics knowledge for the in-tended recognition task. These
models can be dynamically modified according to the
characteristics of speech to be recognized during the training
process.
37. ๏ Acoustic pattern recognition analyses the similarity
between an input speech and a reference mode
(obtained during training) and finds the best match for
the input speech.
๏ Some popular methods of acoustic pattern matching
are Dynamic Time warping (DTW), Hidden Markov
Modeling (HMM), Discrete HMM (DHMM), Continuous-
Density HMM (CDHMM) and Vector Quantization (VQ).
๏ The language analysis is important in speech
recognition, for Large Vocabulary Continuous Speech
Recognition (LVCSR) tasks.
๏ The speech decoding process should invoke the
knowledge of pronunciation, lexicon, syntax and
pragmatics in order to produce a satisfactory output
text sequence.
๏
38. Speech Synthesis
Speech synthesis is either artificial production of
human speech or decoding of coded speech
parameters to recover the original speech. Some
examples of speech synthesis are generation of
speech signals from the speech parameters
received through the transmission line and
generation of speech signal from input text to a
digital system like computer.
40. Text to Speech Conversion
๏ The process of converting text into speech contains two
levels. The first level consists of text analysis and
phonetic analysis.
๏ The second level is generation of speech signal, which
can be divided
into two sub-levels: the search of speech segments
from a database or the creation of these segments and
the implementation of prosodic features.
๏ Text analysis includes the task of text normalization and
linguistic analysis. In text analysis, the numbers and
symbols are converted to words and abbreviations are
replaced by their corresponding whole words or
phrases, so that the whole text is converted to human
utterance like words.
