1. Michael Lang
Phone: 831-250-7299
Email: MichaelALang@comcast.net
LinkedIn: https://www.linkedin.com/in/langmichaela
Summary  Expert knowledge of high-performance SoC design process with over 20 years
of experience in VLSI design
 Work history includes both technical and management backgrounds
 Technical background includes RTL design and front end implementation
(Synthesis, STA, DFT).
 Expert in both Synopsys and Cadence flows including complete flow
development for DC, PT, RC, and Tempus.
 Strong background in timing closure including:
o SDC constraint generation
o Timing results analysis andpost processing
o Manual and automated ECO development
o Driving design closure across RTL, P&R and DFT teams.
 Highly skilledat scripting in TCL, Perl, and Csh
 Extensive script automation background: post processing & design generators
 Very strong work ethic striving to produce the best possible results
 Native English speaker with strong communication skills
Experience Entropic Communications, San Jose CA
 Entropic Projects
o Cardiff
 4M instance chipin TSMC 28HPC
 Hierarchical design with 50% logic in one sub block and 50% at top
 Owner of all logic synthesis, memory BIST, and STA work
 Cadence/Mentor tool set: RC, Tessent, Tempus
o Other product lines: Bixby, Merlot, Jaws
 Projects range from 3M instances @ 40nm to 500K instances @ 65nm
 Implementations include full chip flat as well as hierarchical bottom up
 Role in each project was Front End Implementation Lead
 Worked closely with RTL, DFT, and P&R teams
 Performed all Synthesis and STA work
 DFT work included ‘Design Side’ – scan, OCC, BSD, MBIST
 Assistedwith ATPG and formal verification where necessary
 Drove all timing closure activity
 Intricate flow control scripting and custom setup & reporting for:
 Synthesis: Synopsys DCT & DCG, Cadence RC & RCP
 STA: Synopsys PTSI, Cadence Tempus
 MBIST: Mentor Tessent (LogicVision), Synopsys SMS (Virage)
 Wrote RTL for top level, pad ring, clock & reset control logic
o Galaxy
 TSMC 28HPL design with 13M instances in 25 hierarchical IP blocks
 Largest project in company’s history at that time
 Technical leadresponsible for all backend activities (RTL to GDS)
 Team consisted of Synthesis, STA, DFT, and P&R disciplines
 Team included28 rotating engineers over 1.5 years (many contractors)
 Management responsibilities includedproject scheduling, tracking,
status reporting, and staffing.
 Entropic Methodology and Scripting
(see next page)
Principal Engineer
2013 to 2015
Senior Staff Engineer
2008 to 2012

2. Michael Lang
Entropic Cont’d
 Entropic Methodology and Scripting
o Corporate Implementation Methodology
 Over a 6 month period, lead a team of 5 engineers to develop a
standard ASIC implementation flow.
 Included the creation of standard Synopsys-based flows for: Memory
BIST insertion, Logic Synthesis, Scan Stitching, P&R, Formal
Verification, and Static Timing Analysis.
 Scripts for all tools were developed from scratch with the focus on
global consistency between tools, easy block configuration, and a high
level of automation.
 Personally crafted Synopsys scripts for: SMS MBIST, Synthesis, STA
 Re-wrote these scripts for Cadence tools when we switchedvendors
o Design Automation
 CreatedPerl script based on Veripool Verilog parser to automatically
generate a top level netlist from RTL IP blocks.
 Wrote a TCL shell script that generated RTL from an Excel spreadsheet
describing all IO pad sharing capabilities. Included multiple functional
& test muxing modes, boundary scan, IO pad configuration, etc.
 Wrote synthesis and STA post processing scripts which build HTML
pages complete with hyperlink detail reports and pop up summaries.
 Other areas include memory compiler automation, .lib generation for
custom macros, and LSF queuing support for all flows.
Principal Engineer
2007
LSI Corporation, Milpitas CA
 Developed Synopsys TCL based synthesis environment for the next generation
65nm HD Audio/Video Codec product. Used on 26 modules.
VLSI Design Manager
2001 to 2006
LSI Corporation, Milpitas CA
 Managed a team of 6 RTL design engineers working on micro-architecture,
RTL creation, synthesis, STA, etc. Generateddetailedprojects schedules and
provided monthly engineering reviews to upper management.
 Coordinated all integration activities leading to the successful tapeouts of
multiple chips in the Domino product line over six years.
Staff RTL Design
Engineer
1998 to 2001
Sr. RTL Design
Engineer
1996 to 1997
C-Cube Microsystems and LSI Logic, Milpitas CA
 Developed the System RISC Audio processor for the Domino product line.
o The processor implements the SPARC V8 instruction set as well as a set
of custom Audio DSP and DMA instructions
o It is a superscalar design issuing two instructions (one V8 and one Audio
DSP) per system clock cycle. Key components include Instruction Cache,
Data Cache, and parallel execution pipelines.
o Owned all aspects of the front end design development: micro-
architecture, RTL, synthesis, and timing closure.
Sr. RTL Design
Engineer
1995 to 1996
Advanced Micro Devices, Sunnyvale CA
 Worked with a team of RTL design engineers to develop a PCI-to-PCI bridge
chip. Wrote Verilog RTL and used Synopsys Design Compiler to synthesize the
async FIFO and datapath portions of the design.
Sr. RTL Design
Engineer
1991 to 1995
Design Engineer
1990
National Semiconductor, Santa Clara CA
 Designedthe disk format control section for an 80 Mbit/sec AT disk controller
chip. Designedin Verilog RTL and synthesizedwith Synopsys Design
Compiler. Performed both RTL and gate level simulations.
Education Iowa State University, Ames IA
 Bachelor of Science Electrical Engineering