Space Codesign's presentation to TandemLaunch with intro to electronics design technology (CAD), EDA industry history and career insights startup versus corporate!

1. Space Codesign Systems Inc.
Electronics Design Automation, Space Codesign
and A So-Called Startup Life
Gary Dare
VP of Technical Marketing
TandemLaunch Lunch & Learn

2. Presenter’s Bio
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Gary Leonard Dare
 Born in Winnipeg, Manitoba
 St. Boniface Hospital
 B.Sc. (EE), U of Manitoba
 Ph.D. (EE), Columbia University
 Bell-Northern Research (Nortel)
 Motorola Labs
 Mentor Graphics
 Space Codesign

3. Electronic Design Automation 101
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From Startups to $5 Billion Industry
 First started as internal DIY CAD tools
• at electronics firms, e.g., IBM, Bell Labs, HP
 Also Academic Research
 1980: 18 SF Bay Area + 5 PDX
 2015: up to 32,000 worldwide
 Nearly US$5 Billion industry

4. 80’s Flashback
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Mentor Graphics first setup year was spent In Tom Bruegger’s living room!

5. EDA Big Three
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Up to 80% of Entire Market

6. EDA SME’s (PME)
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From 1 to 200 Persons in size
X
X
X
Nearly All EDA Innovations come from Startups!

7. Carbon Design Systems Case Study
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Maturity period in EDA: 10-15 Years (Michel Courtoy)
 Founded 2002
• Most founders from Viewlogic (acquired by Synopsys)
 US$29.2 Venture Funding
• $4 Million from Samsung Ventures on 9/12, 2012
• Excludes Founders seed equity (from exit packages)
 Profitable in Year 10
• But not enough …
 See Magma and Jasper DA for more cases

8. Successful Hardware/EDA Exits
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University Technology Transfer
 National Instruments
• Prof. James Truchard (UT Austin)
• Fate: Fortune 100 company
• Present: CEO – “Doctor T”
 AccelChip
• Prof. Prith Banerji (Northwestern University)
• Fate: Acquired by Xilinx, Inc.
• Present: CTO, Accenture
 MIPS
• Prof. John Hennessy (Stanford University)
• Fate: SGI then Imagination Technologies
• Present: President, Stanford University

9. Digital Electronics Design Technology
9
A Capsule History
 Physical (workbench) design
 Schematic Capture
 Language-based Design
 Trends
• Integration  Larger/More Complex Designs
• Analysis  Model Complexity, Computation Time
• Role of software rapidly increasing – even definitive
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10. Language-based Design
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From Hardware to System Level
 RTL (register transfer level) – VHDL, Verilog
• AKA Hardware Description Language (HDL)
• Logical function level of detail
• Larger designs  Longer Simulation/Analysis
Project cycle times lengthening!
 ESL (electronic system level) –
C/C++/SystemC
• Higher level of abstraction
• Lower modeling complexity
• Early phase of design (systemic view)
• Smaller code (up to 10X)  Faster Simulation
• Pre-silicon Software Development Feasible
Startup Advantage:
Most STEM Grads
Know C/C++

11. Space Codesign’s SpaceStudio
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Next Generation ESL Design Technology
 Algorithm / Functional Specification
- Requirements for System Architecture
 Architectural Design Exploration
- Hardware/Software Co-design
- Automation supports HW/SW
Partitioning
- Development of System Architecture
 Implementation
 Focus on System Architects

12. Traditional HW-Centric Workflow
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Methodology Impacts Product Development Cycle Time
• Hardware and Software developed on separate paths
• Long design exploration cycles  late problem discovery
• Long HW Prototype debug (FPGA, Emulation, etc.)
• Virtual Prototyping has improved speed but not approach
• Risks in Integration  Problems prolong time-to-market
Mapped
architecture
Analysis
&
diagnostics
time
HW
architecture
C/C++
application
Weeks!
Integration
SW Devel.
HW Design

13. Henry Ford on Customers’ Needs
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Process Improvement Also Needed
 If I had asked people what they wanted,
they would have said faster horses.

14. SpaceStudio Agile Workflow
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Methodology Improvement Enabled By Next Generation ESL Technology
• Automated transformation of functions between HW and SW
• Reuse the Same Model … Without Recoding
• Fast High Level Simulation  Rapid Virtual Prototyping & Analysis
• Agile Work Flow  Immediate Integration and Problem Detection
• Rapid Design Exploration Enabled!
time
Mapped
architecture
Analysis
&
diagnostics
HW architecture
with
SystemC TLM
layer
Multi-threaded
C/C++
application Minutes/Hours!
SW, HW,
Firmware
Generation
Integration

15. Automation supports HW/SW Partitioning
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Same Functions are Retargeted for HW or SW
Drag + Drop
Configuration 1: All SW Configuration 2:
All SW minus IDCT
 Drag and Drop Mechanism Eases Design Iteration
Iteration
Task
Coprocessor

16. Space Codesign Implementation Flow
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Design Creation from Algorithm to Architecture to Implementation
Elix GenX
Functional
(algorithm)
Implementation
SpaceStudio
Architectural
(design exploration,
hw/sw co-design)
….
C/C++
Specifica
tion
Simtek
SoC Virtual
Platform
CPU Core Models (ISS)
IP Reuse
(Mapping)
High Level
Synthesis
Silicon SoC
SoftwareGeneration

17. Space Codesign in Xilinx Vivado Flow
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Design Creation Front-End for Xilinx Vivado (including Vivado HLS)
Elix GenX
IP
(EDK/ISE)
Synthesis
(Vivado HLS)
Xilinx FPGA
Functional
(algorithm)
Implementation
SpaceStudio
Architectural
(design exploration,
hw/sw co-design)
SoftwareGeneration
….
C/C++
Specifica
tion
Simtek
Xilinx Virtual
Platform
CPU Core Models (ISS)

18. Building Space Codesign
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Incorporated in 2008, Operations commenced in August 2010
 Technology Base
• $1 Million in Research Grants
 University Launch Funds
• Univalor
• MSBi Valorisation
 Industrial Innovation Grants
• NRC IRAP (2X)
• SR&ED
 Business Development Grants
• Quebec MDEIE
• Canada EDC/DEC
 Private Placement
Canada Economic Development
For Quebec Regions (CED/DEC)

19. Corporate versus Startup Careers
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Career Directions from the Presenter’s Own Experience
 Corporate
• Pro: Skills, Market Salary, Benefits Package,
Industry Knowledge
• Con: Bureaucracy, Slow Advancement,
Company Consolidations, “Dilbert” Stuff
 Startup
• Pro: New Technology, Fewer Obstacles,
Rapid Advancement, Equity Pop
• Con: Skills, Culture
 Risk: Equal!!!