CISC & RISC Architecture Processors

1. 20051426
Abstract
RICS vs. CISC raged in 1980s when the chip and processor design complexity were principle
constrains to desktop and server computing background. The principle design of computing
significantly growth in desktop and mobile industry using desktop ARM system and for the
laptops running x86 CISC technology. In this report the history of CISC and RISC architecture is
discussed with its suitability on usage. Further the report elaborates on its design pattern,
compiler translate statements in (HLL), functional and non-functional requirements. The industry
situation has been discussed on the period with its effects on pricing strategy and the timely
evolution of system architecture.
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Table of Contents
Abstract ............................................................................................................................................1
1 CISC & RISC Architecture Processors ..............................................................................................3
1.1 Complex Instruction Set Computer .............................................................................................3
1.2 Reduced Instruction Set Computer..............................................................................................3
1.3 Debate of Design Patterns ..........................................................................................................4
1.4 Impact of Historical Framework Design, Architecture Process and Technology on Complex
Instruction Set Computer .................................................................................................................5
1.5 Impact of Historical Framework Design, Architecture Process and Technology on Reduced
Instruction Set Computer .................................................................................................................7
2 The Comparison of CISC and RISC Architecture Designs ................................................................ 10
3 Conclusion .................................................................................................................................... 13
4 References..................................................................................................................................... 15
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1 CISC & RISC Architecture Processors
1.1 Complex Instruction Set Computer
The Complex Instruction Set Computer architecture contains large number of set instructions
which use assemble language level in early stages. The data transaction time was very slow
because the programming was done by assembles language and due to low memory capacity.
The memory in CISC system is comparatively slow but the main memory used on set of
instructions reprocess is 10 times faster. The High Level Language allows the programmer to
create algorithms more concisely which support in-detail
object- oriented design patents. CISC
characteristics give general purpose registers
which has many addressing modes. E.g.: Intel
x86, IBM Z series Mainframe computers can take
CISC architecture process.
Figure 1 CISC Processor
1.2 Reduced Instruction Set Computer
Reduced Instruction Set Computer architecture supports HLL simpler. More complex type of
RISC microprocessor provides less instruction (faster instruction decoding) details and faster
executes time. Computers of earlier stages use only 20% of instruction sets for all the tasks. For
RISC circuits few transistors are needed which provides cost effective,
less heat and simple design with the reduced instruction set
computers.[1] As examples Power PC, Motorola 68000 and Sun Sparc
could be taken as such created by RISC process.
Figure 2 RISC Sun Sparc
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1.3 Debate of Design Patterns
The importance of two design patterns needed to take into consideration to develop set of
instructions, aspects which are performed on point in time: thus each design approach is
applicable to RISC and CISC architecture and its limitations will be considered with key
understanding. The key features, specification and benchmarks will require historical
background. The historical background of RISC and CISC were developed in early 60’s and
80’s with the art of memory, very large scale integration and compliers used to build faster
machines.
On early stages the usage purpose of Storage/ Memory Technology computers were only as core
memory magnetic tapes for storage program. This again incurred high costs and brought off slow
performance. Through introduction of Random Access Memory the performance rapidly
increased in comparison to tapes. But the price of the
RAM was still high; the secondary storage took more time
and got obstructed in many ways. The high cost of the
main memory and low secondary storage was a
challenging issue to expand the code. [2] The best way was
to fit small amount of memory for RAM, counted for
sharing overall cost of the system. In 90’s RAM accounted
for 36% of total system cost and after this RAM became
cheaper and more affordable to the market.
Figure 3 High Level Language Structured
The compiler translate statements in “HLL” like C programming and PASCAL, into the
assemble language. Then the assemble language is converted in the machine code, and there it
took a considerable time to provide output. The difference between operations provided in a high
level of computer architecture: the gap included compiler complexity and execution inefficiency.
“Something to keep in mind while reading the paper was how lousy the compilers were of that
generation. C programmers had to write the word "register" next to variables to try to get
compilers to use registers.” [3]
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The scope of the Very Large Scale Integration “VLSI” became declining in industry
environment. Since 1981 Patterson & Sequin proposed the first RISC architecture process. There
were a million transistors in one chip, transistors resources and CISC machines had function of
units in build numerous chips. The drawback of these chips were power consumption delay,
limited performance in data transferring process, high cost and heat generated.
1.4 Impact of Historical Framework Design, Architecture Process and Technology
on Complex Instruction Set Computer
Early in 60’s and 70’s the hardware market became less attractive economically: in contrary
software market was predicted to increase. The idea of the complexity of software to hardware
domain resulted the CISC creation. Some authors suggested implementation programs and
compilers to their workout to keep semantic gap between high level languages and assemble
language. So the assembler makes their codes in C and PASCAL languages. [4]
Programmers started on promoting HLL in CISC for following reasons,
 Reduce the total system maintenance cost
 Reduce the software implementation cost and save time for software developers
 Decreasing semantic gap between programming and assemble language
 Accuracy and efficiency
 Easy debugging and easy to write compilers
The methodology of increasing performance brought about the need for complexity from
software to hardware and to make high performance at an affordable value. Increase in
performance reduces the time taken to run the program. When CISC machine tries to decrease
amount of the time, the number of instruction set per program to execute preforming task will
vary and that will increase real perform timing.
An example on how to drives increasing complexity of machine instruction sets in CISC
architecture is discussed on the following. There take cube 30 and store it as variable. For the
purpose a code which is written by Hypothetical High Level Language (H) is taken. The H
translates to assemble to ARS stand. There MOVE destination register to another register which
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the way. As MOVE [E, 7] thee number 7 replaced in register. “people would accept any piece of
junk you give them, as long as the code worked part of the reason was simply the speed of
processors and the size of memory” [David A. Patterson]
Figure 4 Addressing Modes
MOVE [E, F]: takes number stored in F and place in E. MUL multiply register take instruction
from destination register and multiply register and place it in destination registers. MUL [A, 50]
the value of A by 50 and that a part A result. MUL [A, C] this multiply A by the value of C and
place in result on D.
When it comes to technology, background of microprogrammings is significant innovation of the
system architecture to implement direct execution. The machine fetches instructions from the
memory locations in control unit (CU). CU input instructions are carried to machine floating
point. There the direct execution conformed the features of adding, shifting and normalization. If
the instruction execute every time it need more space, thus if the instructions size gets large and
complex, it takes lot of task to execute. The direct execution of instruction process has a limited
resources capacity. The ROM helps to control the memory and makes MM fast faster than main
memory. The technology improves with the addition of more functions resulting software faster
to cheaper than hardware.
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1.5 Impact of Historical Framework Design, Architecture Process and Technology
on Reduced Instruction Set Computer
By 1981the technology has changed, but the system architecture concept still remained from
software to hardware. The CISC implementation is complex and it cannot be crossed with
multiple circuits -not ideal. As result there was need of combining everything into one chip and
CPU came to the picture. To overcome the increased processing time, optimized system to do the
task in less time period was required. As turn out compiler technology got smooth and memory
was at a low cost, that drove to design complex instruction sets add to High level language
supported better software. [5]
Figure 5 RISC Architecture Structure
When RISC function come to over board the first thing microcode engine decorative instructions
through the programming code make compiler to their job easier. The indications of reducing
instruction sets liberate most essential information reduce and design user friendly systems in
term Reduced Instruction Set Computer. Introduction of RISC gives small chips with low cost,
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faster data transaction and more reliable direct performance to control the process. The number
of instructions reduced and the size of the instructions also reduced in assemble language to
complete one single cycle. The reason of these decisions based on research resulted microcode
instruction sets. The memory stored instructions and which could be used in assemble: further
many RISC instructions act as CISC machine. The average number of cycles increases which
help to execute machine instruction very operative way to run the program codes.
The pipeline takes an effect on when CPI performance, getting equal and increase considerably.
Addition of pipeline to other features, increasing number of instruction set in given program has
dropped the reduction per cycle instruction sets. In adding there were two key elements which
have been used to design pipeline in RISC- CPI and code bloat exclusion of composite quantity
of registers. The Reduced Instruction Set Computer has register process and LOAD/STORE
access memory. When data represent in LOAD instruction sets, using load operands memory it
registers. In other hand register exist to register represents MUL, STORE instructions sets using
result back to the memory. As a result instruction number sets increases which in turn make
memory usage and technology performance would be significantly increased.
Figure 6 RISC Pipeline Structure
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The HLL application profile code was used most frequently on operands in program thus the
subroutine load in to the registers, need purpose and hypothetical machines were used to carry
out load and store in memory to memory operations. This mean the ARS encounters the MUL
values of [2:4] , [6:8] the microcode translate these instructions set, [6]
I. LOAD 2:4 address in to registers
II. LOAD 6:8 address in to registers
III. MUL two registers address
IV. STORE 2:4 as result
The LOAD and STORE process multiple cycles in RISC architecture machine addresses
patterns. There is a difference between those two cycles: one change MUL instruction sets and
MUL results written by ARS program register address in. The LOAD and STORE secured in to
the MUL instruction, the complier cannot rearrange which result extreme efficiency. In RISC
architecture it has separate LOAD and STORE instruction sets to do their operation, in same
time this result a delay in cycles to load the data to the cycles in the registry.
The key element of one of the innovation in CISC system architecture to implementation
hardware products was Microprogramming. This helps direct execution of machine-fetch cycle
from the memory location to control unit. CU input data and process data converted to
information is then carries out machine fetch cycle floating point using ADD variable to direct
execution. It should be made sure that adding, shifting and normalization to complicit. The main
positive points are faster direct execution and no data transaction obstacles. The cons are the bit
size of the length is high. This results in the lengthening of instruction capacity to execute the
program. Inside micro programming, the controller is in microcode engine to execute the fetch
instructions. The CPU designs how to write microcode programs and how to store in memory
locations. There subroutine communicate on functionality of this program using growing
instruction sets values. Performance in high level and reduction of the memory cost had great
impact for this micro program chips. The disadvantage of this micro code had to debug because
the programs very large scales to elaborate microcode in control unit.
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Figure 7 Addressing Modes
Above managing memory access locations are different on RISC and CISC machine architecture
models. The RISC try to complier operands in the register to register, compilers try to determine
the memory addressing mode to add instructions to memory locations. The general terms to
design RISC prefers to desire register to register execution compilers which used to access. The
LOAD and STORE memory access is then being fetch, as a result memory to memory
architecture introduced by Patterson.
The success of the RISC machines depended on the system intelligent, improving roll of
responsibilities and compiler the codes. The compiler uses code high performance from
hardware to make developments in RISC. The hardware has simple process where as the
software engaged is more complex, both require the code and a minimum of registers to expand
register count. Thus RISC was developed with fewer transistors to create chips, less heat and low
cost advantages, which made it more appealing towards the modern society.
2 The Comparison of CISC and RISC Architecture Designs
It could be seen that initially “CISC” and “RISC” were both simple model where as they have
now evolved into more complex models with the requirement from the modern IT infrastructure.
The following is summary of RISC and CISC architectures features and there development
design decisions towards CPU make. The side by side comparisons brings about these two
architectural aspects focused on performance, price and design strategy. [7]
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CISC Architecture RISC Architecture
Performance Strategy
The performance was enhanced in
interpretation of the program structure. There
compilers ranges were more advantageous on
creating modifications process. The hardware
structure was more complex that makes to
identify chip to understand the program.
Reduced numbering sets in given instructions
and for one chip has transistors were lesser to
produce the program. The program execute
time was fast, hypothetically the speed
increase. The less instruction sets makes them
very efficient to write software with less
resource.
More addressing modes means to
implementation registers has lengthy
instruction codes.
The addressing mode was simple with less
than four codes to implement the sets
Pricing Strategy
Price different complexity to software to
hardware.
Price different complexity to hardware to
software.
Design Strategy
The instruction sets access memory to memory
and straight adding data two memory location
for each sets.
 LOAD/STORE instruction
 Memory location register to register.
The large instruction sets include performing
tasks which have many cycle instruction in
micro code statements in High Level Language
The single cycle instruction sets performance
of basic task function in direct execution
control unit to instruct CISC machines.
Mainly used on desktops, servers and
workstations in CISC platform.
Real time application process will run RISC
platform.
CISC execute time by time reduce total
number instruction programs.
In RISC reduce total number of instruction in
clock rate cycle time.
Example for CISC architectures Intel x86, IBM
Z series Mainframe computers
Example for RISC architecture Power PC,
Motorola 68000, Sun Sparc
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The above list takes many features of RISC and CISC architectures to explain how registers
structure, software supports for HLL and LOAD/STORE set addressing. CISC architecture is
used by ISA to programmers for the implementation of programming codes. The branch
execution prediction wasn’t in operation in 1981. The features that include in branch execution
added complexity to the hardware chip, which in turn resulted high performance. Once again it
should be noted that the matter of high performance not principle of RISC.
The current RISC architecture examples could be given from MIPS, SPARC and G3 which are
all called in Fast Instruction Set Computing (FISC), how special purpose which all include cycle
time can be kept down thus new RISC reduce the cycle time for each machine. For example if,
number of instructions was never reduced, but individual instructions reduced their cycle time
and the complexity of the machine structure. As an example: Mac users who used more G3
instructions sets for RISC circuits. “ A new computer design evolved optimizing compilers
could be used to compile normal programming languages down to instruction that were as
creative in large virtual address space to make instruction cycle time fast as technology would
allow. There machine would have fewer instruction reduced set and remaining of instructions
would generally execute one per clock cycle in reduced instruction set computers.” [8]
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3 Conclusion
The memory and storage devices can make data transaction speed faster and pricing more
economical. When installing programs a lot of companies consider their code bloat question: the
code size gets larger when passing instruction CISC platforms. In the same time RISC processor
gets instructions in extraordinary of variety of memory which are used to increase the design of
this platform. The number of transistors is counted on a higher rate: this problem is overcome by
fixing all transistors into the one silicon chip.
Figure 8 Addressing MIPS ARM Instruction
Compiler and memory access architecture are functional in modern design strategy. The
designers look for possibilities on integrating to create transistors. Reduction of cost and real
time performance has been considered on RISC for direct result to increase high level task of
transistors into designs. In RISC transactions use MIPS and Ultra SPARC architectures whereas
CISC uses ARM and Intelx86 architectures. Both chips mainly contain similar features but RISC
processor has details. Comparing CISC X86 ISA amounted to hardware simulation to transfer
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instructions. Main key elements of RISC features are LOAD/STORE memory access types,
pipeline structure, reduced instruction structure and register to register transaction data methods.
In the end of CISC and RISC discuss the historical development and currently
they are applied with MIPS, Ultra SPARC, ARM, Intelx86 and
LOAD/STORE. Now the modern technology climbs top of the market segment
and each type has different solutions. The modern architecture which makes
breaking decision to optimized Explicitly Parallel Instruction Computing
EPIC. This has “Itanium” processor 9500 series advanced design architecture which supports
pipelines, core threads, and memory (DRAM) instructions sets performance high frequency
clock rates. This Explicitly Parallel Instruction Computing architecture suggested developing the
new implementation for hardware and software.
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4 References
1. John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative
Approach, Second Edition. Morgan Kaufmann Publishers, Inc. San Francisco, CA. 1996.
Page 10
2. David A. Patterson and Carlo H. Sequin. RISC I: A Reduced Instruction Set VLSI
Computer. Computer architecture (selected papers), 2001, Pages 216 – 230
3. John L. Hennessy and David A. Patterson, Computer Organization and Design, Third
Edition: The Hardware/Software Interface. Morgan Kaufmann, 2005 , Pages 491 – 493
4. John L. Hennessy and David A. Patterson, Computer Organization and Design, Third
Edition: The Hardware/Software Interface. Morgan Kaufmann, 2005 , Pages 491 - 493
5. David A. Patterson and D.R Ditzel. The case for the reduced instruction set Computer
architecture (selected papers), 1980
6. John L. Hennessy and David A. Patterson, Computer Organization and Design, Third
Edition: The Hardware/Software Interface. Morgan Kaufmann, 2005 , Pages 588
7. Gerritsen, Armin: CISC vs. RISC. http://cpusite.examedia.nl/docs/cisc_vs_risc.html
8. “A new computer design evolved optimizing compilers could be used to compile normal
programming languages down to instruction that were as creative in large virtual address
space to make instruction cycle time fast as technology would allow. There machine
would have fewer instruction reduced set and remaining of instructions would generally
execute one per clock cycle in reduced instruction set computers.”
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