Managing register banks in the cloud with airhdl
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The slides for my talk at FPGA Kongress 2019 about airhdl, a web-based AXI4 register generator.
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Managing register banks in the cloud with airhdl
- 1. Managing Register Banks in the Cloud with airhdl Guy Eschemann 1FPGA Kongress 2019
- 2. About me • Electrical Engineer (INSA-Lyon, France) • 19+ years of experience in FPGA design • Self-employed FPGA consultant from 2009 – 2019 • Current: Embedded Software Developer at ATT Nussbaum Prüftechnik GmbH • Interests • FPGA design and verification • Embedded systems development • EDA tool development 2FPGA Kongress 2019
- 3. About airhdl • Web-based register generator • Started 2015 as an experiment • Needed the tool for my FPGA consulting work • Arguably one of the first web-based EDA tools ever 3FPGA Kongress 2019
- 4. The Need for Register Banks 4FPGA Kongress 2019
- 5. Caveats • Register banks are the hardware/software interface • Used by HW and SW developers • Many different views (RTL, C, documentation, XML) • Consistency is key • Register definitions change all the time • Must be easy to modify 5FPGA Kongress 2019
- 6. Register Management Strategies • Write everything by hand • Ad-hoc scripts • XML-based generator • Web-based generator 6FPGA Kongress 2019
- 7. The airhdl Solution • Create register map in your browser • Populate with registers and fields • Download generated code • Integrate into your project 7FPGA Kongress 2019
- 8. Benefits • No need to install anything • No need for license files/servers/dongles • Very easy to use (GUI) • Register maps stored in a central place (database) • Easily keep track of revisions • Easy collaboration • Can be accessed from anywhere 8FPGA Kongress 2019
- 9. What’s in a Register Bank • Interface Logic • Registers • Fields 9FPGA Kongress 2019
- 10. airhdl Data Model • Register Maps • Registers • Fields 10FPGA Kongress 2019
- 11. Register Map • Identifier • Base address • Revision ID • Contains one or more registers 11FPGA Kongress 2019
- 12. Register • Identifier • Address offset • Access mode • Write-only • Read-only • Read-write • Interrupt • Contains one or more bit fields • Register types: register, array, memory 12FPGA Kongress 2019
- 13. Field • Identifier • Bit offset • Bit width • Reset value Note: fields inherit access mode from parent register 13FPGA Kongress 2019
- 14. Example Register Map • Control register • Access: read/write • Fields • Ena: 1 bit • Status register • Access: read-only • Fields • Value: 8 bits • Interrupt register • Access: interrupt • Fields: • Done: 1 bit 14FPGA Kongress 2019
- 15. Generated Code: RTL 15FPGA Kongress 2019 entity demo_map_regs is generic( AXI_ADDR_WIDTH : integer := 32; -- width of the AXI address bus BASEADDR : std_logic_vector(31 downto 0) := x"00000000" -- the register file's system base address ); port( -- Clock and Reset axi_aclk : in std_logic; axi_aresetn : in std_logic; -- AXI Write Address Channel s_axi_awaddr : in std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); -- sigasi @suppress "Unused port" s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; ... -- AXI Write Response Channel s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; -- User Ports control_strobe : out std_logic; -- Strobe signal for register 'control' control_ena : out std_logic_vector(0 downto 0); -- Value of register 'control', field 'ena' status_strobe : out std_logic; -- Strobe signal for register 'status' status_value : in std_logic_vector(7 downto 0); -- Value of register 'status', field 'value' interrupt_done_set : in std_logic -- Set signal for register 'interrupt', field 'done' ); end entity demo_map_regs;
- 16. Generated Code: C Header 16FPGA Kongress 2019 /* Revision number of the 'demo_map' register map */ #define DEMO_MAP_REVISION 6 /* Default base address of the 'demo_map' register map */ #define DEMO_MAP_DEFAULT_BASEADDR 0x00000000 /* Register 'control' */ #define CONTROL_OFFSET 0x00000000 /* address offset of the 'control' register */ /* Field 'control.ena' */ #define CONTROL_ENA_BIT_OFFSET 0 /* bit offset of the 'ena' field */ #define CONTROL_ENA_BIT_WIDTH 1 /* bit width of the 'ena' field */ #define CONTROL_ENA_BIT_MASK 0x00000001 /* bit mask of the 'ena' field */ #define CONTROL_ENA_RESET 0x0 /* reset value of the 'ena' field */ /* Register 'status' */ #define STATUS_OFFSET 0x00000004 /* address offset of the 'status' register */ /* Field 'status.value' */ #define STATUS_VALUE_BIT_OFFSET 0 /* bit offset of the 'value' field */ #define STATUS_VALUE_BIT_WIDTH 8 /* bit width of the 'value' field */ #define STATUS_VALUE_BIT_MASK 0x000000FF /* bit mask of the 'value' field */ #define STATUS_VALUE_RESET 0x0 /* reset value of the 'value' field */ /* Register 'interrupt' */ #define INTERRUPT_OFFSET 0x00000008 /* address offset of the 'interrupt' register */ /* Field 'interrupt.done' */ #define INTERRUPT_DONE_BIT_OFFSET 0 /* bit offset of the 'done' field */ #define INTERRUPT_DONE_BIT_WIDTH 1 /* bit width of the 'done' field */ #define INTERRUPT_DONE_BIT_MASK 0x00000001 /* bit mask of the 'done' field */ #define INTERRUPT_DONE_RESET 0x0 /* reset value of the 'done' field */
- 17. Generated Code: Documentation 17FPGA Kongress 2019
- 19. Demo Platform • Enclustra Mercury KX1 FPGA module • Enclustra Mercury+ PE1 baseboard FPGA Kongress 2019 19
- 20. Enclustra FPGA Manager More information at https://www.enclustra.com/en/products/fpga-manager/ FPGA Kongress 2019 20
- 21. Demo Design FPGA Kongress 2019 21
- 22. FPGA Kongress 2019 22
- 23. Demo Design • Emulating user logic using Virtual I/O FPGA Kongress 2019 23
- 24. Wrap-Up FPGA Kongress 2019 24
- 26. Future Work • Generate other documentation formats • Support other memory-mapped interfaces (e.g. Avalon, AHB/APB) • Self-hosted version • See https://airhdl.uservoice.com/forums/279130- airhdl-feature-requests for other ideas 26FPGA Kongress 2019
- 27. Try it Out • Register for free at https://airhdl.com • Let me know what you think! 27FPGA Kongress 2019
- 28. Contact Guy Eschemann noasic GmbH Bankstr. 7 77694 Kehl / Germany E-mail: guy@noasic.com Twitter: @geschema LinkedIn: https://www.linkedin.com/in/geschemann 28FPGA Kongress 2019