1. GEORGE BATES
Address: 127 Gales Drive, New Providence, N.J. 07974
Cell Phone: 973.476.3642 E-mail: george@batesonline.us
IT PROFESSIONAL
IP-BASED NETWORKS AND MOBILITY PRODUCTS INTEGRATION / DEVELOPMENT ž SOFTWARE SYSTEMS MAINTENANCE
ž APPLICATION ANALYSIS, TEST, AND IMPLEMENTATION ž PROBLEM RESOLUTION
Highly skilled, creative and resourceful IT professional, accomplished in designing, developing, and delivering cost-effective
technology solutions. Possess strong qualifications in all facets of project life-cycle development. Strong ability to follow project
from initial feasibility analysis and conceptual design through documentation, implementation, user training, quality review, and
enhancement. Proven capacity to resolve complex problems, assess situations, and quickly decipher the necessary course of
action.
 Extensive experience with Network analyzers such as, WIRESHARK, and RADCOM performer, Spirent Adtech
AX4000, and Spirent Test Center , JDSU DNA, Spirent VR5 and SR5500, ERCOM MOBIPASS EPC CORE
Simulator
 Expertise in test equipment related to hardware troubleshooting and design tasks. Hardware experience includes
knowledge and skills in most advanced, high speed Digital circuitry, Digital Logic Analyzers, Spectrum analyzers (HP,
Agilent), Digital Storage Oscilloscopes, Analog Oscilloscopes, Vacuum Tube Volt Meters, Digital Multi Meters, Signal
Generators, Programmable Power Supplies, and AF / RF circuitry
 In-depth router MLS and L2 switch configuration experience. Worked regularly with Cisco 6500 and 10000 series,
Juniper M40e, m10i series routers, RIVERSTONE 8600 MLS, Alcatel-Lucent 7750, 7710, 7705, 7450, enterprise omni
switches and Lucent DMX products.
Professional Experience
Alcatel-lucent, Murray Hill, NJ
LTE Small Cell Feature Integration: Transport Test Lead – Multi-Standard Cell Current
Lead team through software release cycle with expertise in test plan creation, requirements traceability and software design
compliance. Technical Mentor and team lead for Ethernet, IPv4 and ipv6, IPSEC transport testing in support of SON PNP
verification.
 LTE E2E network verification for s1C,s1U,x2C,x2U
 dhcp and dns protocol compliance verification
 Ethernet, IPv4, IPv6, IPSEC protocol compliance verification.
 QOS/COS verification, QCI, linux netfilter, DSCP, 802.1P
Designed, implemented and maintain the small cell feature integration lab.
 Engineered IPv4, ipv6 address plan for all LTE network elements in support of Small cell feature integration test
effort.
 Integrated and configured backhaul router and switch network to LTE EPC Core.
 Integrated and configured ESXI VMWARE servers homing Linux fedora VM images. Configured these images to
simulate numerous server types needed for SON PNP verification. Servers include:
o DHCP ,DNS , Strongswan IPSEC SEGW, CMS, AAA, UMTS CORE simulation.
Alcatel-Lucent, Murray Hill, NJ
LTE Small Cell System Test: System Test Engineer – VZW Metro Cell Outdoor 2012-2014
L1/L2 modem verification in support of initial cell setup and call setup proof of concept. Work closely with L1/L2 modem
Developer’s to pin point and report issues regarding LTE protocol stack physical, transport and logical channels,
Documented and presented technical lectures on VZW MCO low level trace tools and diagnostic methods.
Train test community from various locations throughout the world.
Designed and implemented numerous lab automation tools used by small cell community.
Responsible for verifying the following LTE Features:
 IP Transport, IRAT and EMCTA, DL Link Adaptation, PUSCH FPC, CAC/911,
Received CEO Recognition award for year 2013
Alcatel-Lucent, Murray Hill, NJ
LTE SYSTEM TEST: System Test Engineer – MACRO CELL 2009-2012
Lab planning, automation and equipment integration.
Integrated and administered 2 ERCOM MOBIPASS EPC CORE SIMULATOR CHASSIS.
Verification of the following features:
 Transport ipv4/ipv6, LTE-EVDO I-RAT, CDMA CSFB, EMCTA, EUTRAN SHARING, UL Fractional Power Control

2. GEORGE BATES
Address: 127 Gales Drive, New Providence, N.J. 07974
Cell Phone: 973.476.3642 E-mail: george@batesonline.us
Alcatel-Lucent Technologies, Whippany, NJ
Transport Integration Feature Tester 2004-2009
Develop functional and regression test plans, and perform root cause analysis to ensure successful integration of CDMA and
EVDO technology into IP/ETH-based backhaul network, specializing in Network and Fault Detection integration and validation.
 Captured software defects and recommended innovative testing methodologies, verification systems, and networking
tools
 Streamlined the debugging process and evaluation of test data, as well as expedited identification of root causes
through meticulous documentation and recording of useful information from test results and defects
 MPLS (LDP), BFD, VRRP, HSRP, SSO and NSF, APS fault detection protocols.
 Worked with protocols such as:
Layer 1: T1, SONET, Ethernet, I2C, ARCNET
Layer2: 802.3/802.1 LAN protocols, MLPPP and PPP, Frame Relay, HDLC
Layer3: IP Routing(OSPF,BGP)
Layer 4:TCP, SCTP and UDP
Laboratory Manager 2006-2008
Oversaw and monitored efficiency in daily laboratory functions. Resolved laboratory-related problems and organized laboratory
schedules. Documented and ensured accuracy in equipment interconnects and configurations. Planned, engineered, purchased,
and implemented new cell sites, MSC, IP Network, network test equipment, and laboratory automation tools.
 Spearheaded research, planning, and implementation of the EDENTREE Lab Management Software and MRV layer 1
switching unit.
 Greatly reduced the required time in setting up lab sessions for users by designing numerous TCL and TK tools
 Regarded as the key troubleshooter for the IP backhaul and Ethernet Backhaul product, which received an award for
addressing and resolving complex problems.
 Strategically developed the IP Backhaul troubleshooting guide and delivered the materials in a live training session to
the Lucent worldwide services team.
 Analyzed the application using CAIT and QXDM analysis tools. Obtained significant knowledge in EVDO call
processing application.
 Promoted to member of technical staff for numerous accomplishments.
System Software Test Engineer 2002-2003
 Verified and maintained the overall system integrity for TDMA / CDMA coexistence feature. Processed and ensured
efficiency of system level call loads and verified system level data (service and plant measurement) based on system
requirements.

3. Consulted by a newly formed team responsible for the integration of the CDMA application onto all IP/ETH backhaul network in
2003. Performed analysis of End to End application Data under network Fault scenarios, as well as EVDO REVA intra and inter
RNC Hand off scenarios. Facilitated CDMA and EVDO cell performance testing; all tests efforts involved understanding of
application down to the message (packet) level in order to validate resultsGEORGE BATES
Address: 127 Gales Drive, New Providence, N.J. 07974
Cell Phone: 973.476.3642 E-mail: george@batesonline.us
Technical Staff 2001-2002
 Functioned as lead hardware designer for two circuit packs prior to moving to the FLEXENT TDMA software test
team.
 Guaranteed the reliability of the newly built software by running a set of regression tests to validate software loads.
Estimated time intervals for various test periods in partnership with project team to enable appropriate reporting and
management of the feature schedule.
 Ensured that all requirements test cases were documented properly, lab equipment installation was planned, and risk
assessments were noted. Thoroughly examined the document with key team members to assure full product
verification.
Lead Designer / Senior Technical Associate / Hardware Technician 1998-2001
 Appointed to serve as lead designer for the upcoming hardware project after working initially as a Hardware Technician
for six months. Also served as senior technical associate responsible in debugging of circuit packs for the Flexent
TDMA product line.
 Developed a circuit pack from conception to finished product (Enhanced TDMA oscillator Module), which included
working on requirements with the systems engineers, overseeing details of the circuit design, and drawing out the
schematic. Used VHDL hardware description language for the logic design of CPLD and FPGA.
 Built the board prototypes after the review of the circuit pack design, which involved coordinating with Parts
Procurement Team and Parts Vendors in order to purchase the electronic components for the circuit pack. Ensured
that integrity of the electronic design was properly transferred to blueprint. Examined the circuit pack blueprint,
wrote the unit test plan, and tested the prototype boards based on the test plan, then modified as necessary.
Resolved all issues on hardware integration and software test cycles. This initiative resulted in promotion to member
of technical staff position.
Earlier Experience
Tech Manager, 1990-1997
Triple S Electronics (a professional audio repair and installation company), Belleville, NJ
Studio Technician, 1989-1990
Electric Lady Studios, New York, NY
Radio Operator, 1983-1987
United States Marine Corps
Education
RECORDING STUDIO ENGINEERING PROGRAM, 1988-1989
The Institute of Audio Research, New York, NY
Professional Training
Lucent Technologies
Digital Logic Design ¡ High Speed Digital Design ¡ C++ programming course ¡ Introduction to Object oriented programming
¡ PCS and Cellular Networks ¡ TDMA (is-136) standards ¡ CDMA (is-95) standards ¡ UMTS (IMT-2000) 3GPP standards
¡ EVDO (CDMA-2000) 3GPP Standards ¡ CCNA Certification Course (hosted by Lucent Technologies)
¡ Juniper Networks Troubleshooting Course (hosted by Lucent Technologies) ¡ Riverstone Networks product line
(Hosted by Lucent Technologies) ¡ VHDL hardware description language programming
Awards and Honors

4. Received numerous awards including CEO RECOGNITION AWARD 2013.
Activities
 Instituted an outdoor club for Lucent Technologies in 2001
 “Self Expression and Leadership” Landmark Education