M 02.8 rev02 capitolato tecnico di fornitura technical specifications

CAPITOLATO TECNICO DI FORNITURA M 02.8
TECHNICAL SPECIFICATIONS
2/4/2019 Revision 01
TEKUBE SRL | Partita IVA e codice fiscale: 02932880301 | Iscrizione REA n° UD-299226 | Data iscrizione: 26/06/2018
Sede legale e sede operativa: Via Galileo Galilei 16, 33010 – Tavagnacco (UD) – Italia | www.tekube.com info@tekube.com

INDEX
1. Base materials ...................................................... 4
1.1 Multilayerand microviaboards ................................... 4
1.2 Plated-through printed circuit boards ........................... 5
1.3 Rigid-flex printed circuit boards .................................. 6
2. Formats & panel layout .......................................... 7
2.1 Panel layout .............................................................. 7
2.2 Fabrication formats / panel layout ............................... 8
3. Layer stackup ........................................................ 9
3.1 Multilayer boards up to 18 layers ................................ 9
3.2 Microvia boards ...................................................... 10
3.3 Rigid-flex printed circuit boards ................................. 13
4. Design rules ........................................................ 15
4.1 Final thickness tolerances for multilayer
and microvia boards ................................................. 15
4.2 PCBlayout .............................................................. 15
4.3 Annular rings and pad sizes ...................................... 16
4.4 Final thickness of copper plating ............................... 17
4.5 Clearance ............................................................... 17
4.6 Design rules for BGA fan-out .................................... 18
4.7 Design rules and technological spectrum for
rigid-flexPCBs ......................................................... 20
4.8 Controlled impedance PCBs ...................................... 23
5. Solder mask ......................................................... 25
5.1 Solder mask design for vias with chemical surfaces .... 28
6. Surface finishing ................................................. 29
6.1 Partial gold plating with milled
interconnecting line tracks ........................................ 30
6.2 Layout of interconnecting line tracks without
solder masking ........................................................ 30
7. Additional printing ............................................... 31
7.1 Via hole filling / plugging vias ................................... 32
7.2 Peelable solder mask or masking tape ....................... 32
8. Mechanical manufacturing....................................... 33
8.1. Drilling....................................................................................... 33
8.2. Milling....................................................................................... 35
8.3. Scoring...................................................................................... 36
8.4. Chamfering gold ridges.......................................................... 37
8.5. ZIF connectors (Zero Insertion Force)
for rigid-flex PCBs.......................................................................... 38
9.Packaging Guidelines …………………………….. 39
2

1 BASE MATERIALS
1.1 Multilayer and microvia boards
Core Materials
Characteristics Values
Material types FR4 (Tg: 135 °C); FR4 (Tg: 150 °C)
Core thickness (mm) w/o base copper 0.10; 0.125; 0.15; 0.20; 0.25; 0.30; 0.36; 0.41; 0.51; 0.61; 0.76; 1.00
Copper cladding 18 µm; 35 µm; 70 µm; 105 µm
Thickness tol. w/o base copper Acc. to IPC 4101B Class B
Permittivity εr at 1 MHz: 4.6 -4.9
Loss tangent tanδ at 1 MHz: 0.019
Material properties Tg 135 °C Tracking resistance CTI: Level 200
Minimum electric strength: 39 kV/mm
Flammability class: UL 94V-0
Permittivity εr at 1 MHz: 4.95
Minimum electric strength: 49 kV/mm
Prepreg
(FR4 insulating layers between the cores)
Prepreg types 106 1080 2116 7628
Material thickness 50 µm 63 µm 110 µm 180 µm
Permittivity εr at 1 MHz: 4.6 - 4.9
Material properties Tg 135 °C
Tracking resistance CTI: Level 200
Material properties Tg 150 °C
Tracking resistance CTI: Level 500
3

1.2 Plated-through printed circuit boards
Rigid Materials
0.8 mm ± 0.10 mm
1.0 mm ± 0.10 mm
Material thickness with base copper
1.2 mm ± 0.13 mm
1.5/1.6 mm ± 0.13 mm
2.0 mm ± 0.18 mm
2.4 mm ± 0.18 mm
Thickness tol. with base copper Acc. to IPC 4101B Class L
Dielectric strength: 45 kV (material thickness ≥ 0.5 mm)
Dielectric strength:
> 50 kV (material thickness ≥ 0.5
mm)
4

1.3 Rigid-flex printed circuit boards
Rigid Materials
Material type FR4 (Tg: 135 °C)
Thickness in mm with base copper 0.60; 0.80; 1.00; 1.20; 1.50;
Copper cladding 18 µm; 35 µm
Thickness tolerance with base copper According to IPC 4101B Class B
Material properties Tracking resistance CTI: Level 200
Dielectric strength: 45 kV (material thickness ≥ 0.5 mm)
Core Materials
Material types
FNC (epoxide adhesive system)
AP8525E(adhesivelessmaterial)
Material thickness 50 µm
Base copper cladding 18 µm electro-deposited copper
Material properties Dielectric strength: min. 2,500 V/mil
Cover Layers
(“solder masking” of flexible area)
Material types
LF 0210 (acrylic adhesive system)
LF 0310 (acrylic adhesive system)
Material thickness of polyimide 25 µm
Adhesive thickness 50 µm; 75 µm
5

2 FORMATS & PANEL LAYOUT
2.1 Panel layout
In order to make optimum use of the available surface area, it is recommended to design multiple printed panels,
especially for small formats. Allowing for the specifications described below and the usable area defined in section
2.2, there are manifold possibilities to design multiple printed panels. Here are some suggestions:
Separating slit
Scoring
Separating slit
Retaining tab
Scoring
Retaining tab Separating hole
Separating slit
Remaining material
approx. 0.4 mm / 15.7 mil
Diameter of separating holes 0.70 mm /
27.5 mil Retaining tab 4.20 mm / 165.4 mil
approx. 0.5 mm / 19.7
mil approx. 1.10 mm / 43.3 mil
6

2.2 Fabrication formats / panel layout
Usable areas
Product group Max. usable width A Max. usable length B
Multilayer boards 317 mm / 418 mm / 498 mm 543 mm
Microvia boards 418 mm / 498 mm 543 mm
Plated-through PCBs 318 mm / 420 mm / 500 mm 545 mm
HSMtec for high current & heat
317 mm / 418 mm / 498 mm 543 mm
management
Rigid-flex PCBs with 317 mm 543 mm
2 inner flex layers 210 mm 543 mm
Notes
Milled edges Allow for a spacing of 10 mm between the individual PCBs.
Scored edges
No spacing is required between the individual PCBs allowing for a greater usable
area on the PCB.
2-side milling/scoring
In the scoring direction, the usable area of the PCB is larger than with 4-side
milling. Allow for a spacing of 10 mm from milled edges.
2-side milling/ 2-side milling/
4-side scoring 4-side milling scoring, variant 1 scoring, variant 2
A A A A
B B B B
1 2 2 1 1 2
Scored edge Milled edge 1: 0 mm spacing for scoring
2: 10 mm spacing for milling
7

3 LAYER STACKUP
3.1 Multilayer boards up to
18 layers
stackups can be fabricated using the core materials and
prepreg types listed in 1.1 “Multilayer and microvia boards”.
At least two prepreg films shall be arranged between the
copper foils where possible. The minimum thickness of the
prepreg films shall be the thickness of the inner copper foil
+ 50 µm. In the following, the standard stackups for 4, 6 and
8 layers are specified which will be used unless specific
customer requirements for stackups are available.
Final thickness = final thickness of multilayer board
incl. electro-deposited layers and solder masking
Ex: standard 6-layer board, final thickness 1.6 mm ± 10%
Layer 1 -------------------------- Base copper 18 µm
============= Prepreg 2116 110 µm
============= Prepreg 2116 110 µm
Layer 2 -------------------------- Copper 35 µm
////////////////////////////// Core 360 µm
Layer 3 -------------------------- Copper 35 µm
============= Prepreg 2116 110 µm
============= Prepreg 2116 110 µm
Layer 4 -------------------------- Copper 35 µm
////////////////////////////// Core 360 µm
Layer 5 -------------------------- Copper 35 µm
============= Prepreg 2116 110 µm
============= Prepreg 2116 110 µm
Stackup thickness after
laminating 1556 µm
============= Prepreg 2116 110 µm
============= Prepreg 7628 180 µm
Layer 2 -------------------------- Copper 35 µm
////////////////////////////// Core 760 µm
Layer 3 -------------------------- Copper 35 µm
============= Prepreg 7628 180 µm
============= Prepreg 2116 110 µm
Layer 4 --------------------- Base copper 18 µm
laminating 1446 µm
============= Prepreg 2116 110 µm
============= Prepreg 2116 110 µm
Layer 2 -------------------------- Copper 35 µm
////////////////////////////// Core 200 µm
Layer 3 -------------------------- Copper 35 µm
============= Prepreg 1080 63 µm
============= Prepreg 1080 63 µm
Layer 4 -------------------------- Copper 35 µm
////////////////////////////// Core 200 µm
Layer 5 -------------------------- Copper 35 µm
============= Prepreg 1080 63 µm
============= Prepreg 1080 63 µm
Layer 6 -------------------------- Copper 35 µm
////////////////////////////// Core 200 µm
Layer 7 -------------------------- Copper 35 µm
============= Prepreg 2116 110 µm
============= Prepreg 2116 110 µm
laminating 1538 µm
8

3.2 Microvia boards
According to IPC-2226, the term “microvia” refers to the following layout designs:
• Via diameter ≤ 0.15 mm
• Pad diameter ≤ 0.35 mm
selecting the pad diameter in relation to the stackup structure
Aspect ratio max. 1:1
1 x 1080 = 63 µm
≥ 320 µm
This layer must be flooded with copper (e.g. Vcc, GND, …)
2 x 106 = 100 µm
min. 320 µm
≥ 350 µm
3.2.1 Microvia holes combined with through-holes
This is the most cost-effective method of integrating microvias in a board layout. The complete multilayer board
can be fabricated in a single laminating process. Fabrication sequence:
1.Laminating L1 to Ln
2.Drilling through-holes L1-Ln and microvias
3.Plating through-holes L1-Ln and microvias
≤ 125 µm
Microvia from L1 to L2
L1
Prepreg
2 x 106 (100 µm) or
L2
1 x 1080 (63 µm)
Core
L3
Variable stackup with
x layers
prepregs and cores
Ln-2
Ln-1
Core
Prepreg
2 x 106 (100 µm) or
Ln 1 x 1080 (63 µm)
Microvia from Ln to Ln-1
9

3.2.2 Microvia holes combined with buried via cores and through-holes
Fabrication sequence:
1. Drilling buried vias in the cores 4. Drilling through-holes L1-Ln and microvias
2. Plating the buried vias 5. Plating through-holes L1-Ln and microvias
3. Laminating L1 to Ln
≤ 125 µm
L1
Prepreg
2 x 106 (100 µm) or
L2 1 x 1080 (63 µm)
Buried via
Corecore
L3
Variable stackup with
x layers
prepregs and cores
Ln-2
Buried via
Corecore
Ln-1
Prepreg
2 x 106 (100 µm) or
Ln 1 x 1080 (63 µm)
3.2.3 Microvia holes combined with buried vias and through-holes
Fabrication sequence:
1.Laminating L2 to Ln-1
2.Drilling buried vias L2 to Ln-1
3.Plating buried vias L2 to Ln-1
≤ 125 µm
L1
L2
Bur
ied
≥ 225 µm
L3
vias
Variable stackup
fr
o
m
with prepregs
and cores
to
L2
Ln-2
-
L
n
≥ 250 µm
1
Ln-1
Ln
4.Laminating L1 to Ln
5.Drilling through-holes L1 to Ln and microvias
6.Plating through-holes L1 to Ln and microvias
Prepreg
2 x 106 (100 µm) or
1 x 1080 (63 µm)
Prepreg
x layers
Prepreg
Prepreg
2 x 106 (100 µm) or
1 x 1080 (63 µm)
10

Copper plating thickness according to IPC-6012
Hole type
Requirements
Class 2 Class 3
Copper thickness for microvias
12 µm mean value 12 µm mean value
10 µm minimum value 10 µm minimum value
Copper thickness for buried via 15 µm mean value 15 µm mean value
cores 13 µm minimum value 13 µm minimum value
Copper thickness for buried vias
Copper thickness for through-holes
11

3.3 Rigid-flex printed circuit boards
The following shall apply for rigid-flex stackups:
Final thickness = final thickness of compound stackup incl. electro-deposited layers and solder masking
3.3.1 standard stackups with one outer flex layer
2-layer compound stackup; final thickness 0.80 mm to 1.70 mm ± 10% (schematic representation)
25 µm Cover layer
35 µm Solder side
50 µm
40 µm
Variable core thickness
35µm
25µm
Final thickness ± 10%
Solder mask Epoxyadhesive Copper
Variable core thickness in µm 610 800 1000 1200 1500
Calculated final thickness in µm 820 1010 1210 1410 1710
Component side
Polyimide FR4 core
The “core” can be replaced by a multilayer structure.
The following figure shows a possible stackup design.
4-layer compound stackup; final thickness 0.80 mm to 2.00 mm ± 10% (schematic representation)
25 µm Cover layer
Solder side35 µm
50 µm
40 µm
63 µm
63 µm
35 µm Inner layer
200 µm Variable core thickness
35 µm Inner layer
63 µm
63 µm
35 µm Component side
25 µm
732 µm Final thickness ± 10%
Solder mask Epoxyadhesive Copper Polyimide FR4 core/Prepreg
12

Final thickness is determined by the number of layers and film thickness of the cores and the prepregs. Please note that the final
thickness shall always be between 0.80 mm and 2.00 mm! In the standard stackup, the maximum number of layers is limited to 6.
3.3.2 stackup with two symmetrical flex layers
The layers are arranged in rigid-flex-flex-rigid; final thickness 1.40 mm to 1.80 mm ± 10% (schematic representation)
25 µm
Outer layer35 µm
70 µm
Cover layer75 µm
35 µm
50 µm
Inner layer35 µm
75 µm Cover layer
70 µm
35 µm
Outer layer
25 µm
Final thickness ± 10%
Solder mask Copper Polyimide
Variable core thickness in µm 410 510 610
Calculated final thickness in µm 1350 1550 1750
No-flow prepreg FR4 core
The core thickness of the rigid layers must be
identical (symmetrical design)!
13

4 DESIGN RULES
4.1 Final thickness tolerances for multilayer and microvia boards
Base copper on
9 µm to 105 µm
outer layers
Final copper and tolerance
Acc. to IPC 6012 Class 2
(current edition)
Final thickness (incl. final
0.8 mm - 2.6 mm
copper and solder mask)
Tolerances
0.8 mm - 2.0 mm ± 10%
> 2.0 mm - 2.6 mm ± 0.2 mm
4.2 PCB Layout
copper
copper
1 2 3 4
Track- Pad- Pad- Line 4
Base
Final
Track Track Pad width 1
≥ ≥ ≥ ≥
µm µm µm mil µm mil µm mil µm mil 2
1
Inner layers
318 18 75 3 75 3 75 3 75 3
35 35 90 3.6 90 3.6 90 3.6 100 4
70 70 125 5 125 5 125 5 150 6
105 105 200 8 200 8 200 8 200 8
outer layers
9 35 100 4 100 4 100 4 100 4
1: Min. spacing track to track35 70 150 6 150 6 150 6 175 7
2: Min. spacing pad to track
70 105 225 9 225 9 225 9 250 10 3: Min. spacing pad to pad
105 140 275 11 275 11 275 11 300 12 4: Min. line width
14

4.3 Annular rings and pad sizes
Final copper on outer layers
acc. to IPC Class 2
Final copper on inner layers5
1 2
acc. to IPC Class 2
Copper in hole:
• IPC Class 2: min. value 18 µm
mean value 20 µm
• IPC Class 3: min. value 20 µm
6 mean value 25 µm
3 • Specialty class: ≥ 25 µm
4
outer layers
1
Min. annular
Base copper Final copper
ring on outer
layers
µm µm µm mil
9 / 18 35 210 8.3
35 70 235 9.3
70 105 285 11.3
105 140 310 12.2
Inner layers
2
Min. annular
Base copper Final copper
ring on inner
layers
µm µm µm mil
18 18 235 9.3
35 35 235 9.3
70 70 260 10.3
105 105 310 12.2
Examples of correlation between solder pad diameter and final diameter
3 4 5 6
Pad diameter Pad diameter Final diameter Hole Min. annular Final copper Board
on on (tolerance diameter ring around on thickness
outer layer inner layer -0.05 / +0.1 mm) hole diameter outer layer up to
with 35 µm radius on
copper outer layer
mm mil mm mil mm mil mm mil µm µm mm
0.52 20.5 0.57 22.5 0.10 4 0.25 10 135 35 1.6
0.77 30.3 0.82 32.3 0.35 14 0.50 20 135 35 1.6
15

4.4 Final thickness of copper plating
Final thickness of copper plating on outer layers
after machining, according to IPC 6012
Final thickness of copper plating on inner layers
after machining, according to IPC 6012
Base copper
Requirements
Class 2 Class 3
9 µm ≥ 26.2 µm ≥ 31.2 µm
18 µm ≥ 33.4 µm ≥ 38.4 µm
35 µm ≥ 47.9 µm ≥ 52.9 µm
70 µm ≥ 78.7 µm ≥ 83.7 µm
105 µm ≥ 108.6 µm ≥ 113.6 µm
Base copper Requirements
18 µm ≥ 11.4 µm
35 µm ≥ 24.9 µm
70 µm ≥ 55.7 µm
105 µm ≥ 86.6 µm
4.5 Clearance
Clearance means the distance of the hole wall to the inner layer copper.
Definition according to IPC A 600: The distance between the
copper of the inner layer and the copper sleeve shall be lar-
ger or equal 0.1 mm (unless a specific value is defined in the
procurement specifications).
A
Larger values are desirable in any case.
Please note that the minimum clearance between line tracks and
non-plated through-holes (NPT) on outer layers shall be 250 µm.
A
Minimum line clearance
Max. tolerance value of
Drillallowance
Minimum clearance value
multilayer fabrication in customer data related to
final diameter
100 µm 100 µm 75 µm 275 µm
125 µm 100 µm 75 µm 300 µm
150 µm 100 µm 75 µm 325 µm
175 µm 100 µm 75 µm 350 µm
200 µm 100 µm 75 µm 375 µm
225 µm 100 µm 75 µm 400 µm
250 µm 100 µm 75 µm 425 µm
16

4.6 Design rules for BGA fan-out
1
2
8 5
4
11 7
9
6
10
3
Outer layer
Vias
1st inner layer
2nd inner layer
With the dogbone design, vias
have to be positioned in the
square center of the BGA
solder pads. This ensures the
best possible solder mask
design for the solder dam and
hence an ideal solder process.
1 2 3 4 5 6
BGA grid
BGA pad Position of via
Hole diameter
Via pad on Via pad on
(solder pad) pad outer layer inner layer
mm mil mm mil mm mil mm mil mm mil mm mil
1.00 39.37 0.50 19.70 0.500 19.70 0.25 10 0.55 21.60 0.6 23.62
0.80 31.50 0.40 15.75 0.400 15.75 0.25 10 0.50 19.70 0.6 23.62
0.80 31.50 0.35 13.78 0.400 15.75 0.25 10 0.53 20.87 0.6 23.62
0.75 29.50 0.33 13.00 0.375 14.76 0.25 10 0.53 20.87 0.6 23.62
1 7 8 9 10 11
spacing of BGA Line width on Line width on
Inner layer: Inner layer:
BGA grid spacing of via spacing of hole
pad to via pad outer layer inner layer
pad to track to track
mm mil mm mil mm mil mm mil mm mil mm mil
1.00 39.37 0.180 7.00 0.115 4.5 0.150 5.9 0.125 5 - -
0.80 31.50 0.115 4.55 0.115 4.5 0.115 4.5 - - 0.220 8.6
0.80 31.50 0.115 4.55 0.115 4.5 0.115 4.5 - - 0.193 7.6
0.75 29.50 0.100 4.00 0.115 4.5 0.115 4.5 - - 0.193 7.6
17

BGA 0.65 mm grid with 0.4 mm landing pads incl. microvias - 145 balls
1
2
3
4
5
1: Viapad on outer layer 0.55 mm / 21.65 mil
7
62: Hole diameter 0.25 mm / 10 mil 8
3: Line width 0.127 mm / 5 mil
4: Grid 0.65 mm / 25.6 mil
9
5: BGA/landing pad 0.4 mm / 15.75 mil
6: Target pad for MV 0,35 mm / 13,78 mil
7: Spacing on inner layer 0.095 mm / 3.74 mil
8: Line width on inner layer 0.11 mm / 4.33 mil
9: Track width on inner layer 0.115 mm / 4.65 mil
Outer layer 1st inner layer Through holes Microvias
18

4.7 Design rules and technological spectrum for rigid-flex PCBs
4.7.1 Rigid-flex printed circuit board with one outer flex layer
25µm
50 µm
3
4 1
25 µm
Solder mask Epoxyadhesive Copper
3
2
1:Total number of layers 2-6
2:One outer flex layer
3:Min. overlapping of 1 mm (40 mil)
on rigid area. This area must be free
of solder spots, holes and vias.
4:Rigid area / FR4: 0.8 mm - 2.0 mm
Polyimide FR4 core
2
4
5
1 6
1:Min. line width in rigid area: 0.125 mm/5 mil
2:Spacing of copper to edge min. 0.5 mm/20 mil
3:Spacing of copper to edge:
min. 0.3 mm/12 mil for milling
min. 0.6 mm/23.6 mil for scoring (with material thickness ≤ 1.6 mm)
min. 0.7 mm/27.6 mil for scoring (with material thickness > 1.6 mm)
4: Min. line width 0.2 mm/8 mil
5: Min. line spacing 0.2 mm/8 mil
6: Finishing:
• Immersion Ni/Au
• Immersion Sn
• HAL, material thickness ≥ 1 mm
Solder mask Copper Polyimide/masking film Finishing
19

4.7.2 Rigid-flex printed circuit board with two symmetrical flex layers
50 µm 2
35 µm
1
1: Smallest hole diameter: 0.25 mm 2: Thickness: 1.40 mm - 1.80 mm
Solder mask Copper Polyimide No-flow prepreg FR4 core
Rigid area Flex area Rigid area
1: Min. line width in flex area 0.20 mm/8 mil
6 2: Min. line spacing in flex area 0.20 mm/8 mil
3 3: Min. spacing to outline in flex area 1.0 mm
1
4: Min. line width in rigid area 0.20 mm/8 mil
5
5
5: Min. spacing in rigid area 0.15 mm/6 mil
2 4 6: Min. spacing to outline in rigid area 1.0 mm
The radius of the annular ring on the flexible inner layer has to be 350 µm/14 mil bigger than the radius of
the final diameter (huge difference in dimensional stability between FR4 and polyimide material).
Final thickness tolerances for
rigid-flex PCBs
Base copper on outer layer
18 µm and 35 µm
with outer flex layer
Base copper on outer layer
9 µm to 35 µm
with inner flex layer
Final copper and tolerance
Acc. to IPC 6012 Class 2
(current edition)
Final thickness of copper plating: see section 4.4
for further details.
20

4.7.3 Technological information on rigid-flex PCBs
Processing recommendations
• General information:
Rigid-flex polyimide printed circuit boards can be
both hand and machine soldered. The industrial
engineering methods generally used for rigid boards,
such as infrared, convection or vapor phase
soldering, can also be applied to rigid- flex circuits.
• Polyimide films are highly hygroscopic:
A dried polyimide film will again reach its original
moisture saturation level (up to 3 % max.) after only a
few hours. For this reason, it is absolutely vital to bake
(dry) the printed circuit boards prior to soldering.
• Possible errors when baking is omitted:
Failures due to delamination, blistering, tearing, etc.
during soldering caused by the high moisture content
of the poly-imide.
• Recommendation for baking:
Bake (dry) rigid-flex circuits for about 2 hours at 110
°C to 120 °C in a convection oven prior to soldering.
Rigid-flex circuits should be assembled within 6 to 8
hours after baking and stored at a maximum humidity
of 50 % until they are used.
Application guidelines
1.Approximate values for bending radii with cover
layer on flex area
Bending radii with one copper layer in flex
area: Min. radius = thickness of flex area x
5 (corresponds to ≥ 1 mm)
Bending radii with two copper layers in flex
area: Min. radius = thickness of flex area x
10 (corresponds to ≥ 3 mm)
When the flex area is covered with a cover
layer, the copper is in the “neutral zone” which
results in a very good bending behavior.
Solder mask
Copper
Polyimide
FR4 core
Masking film
Bending radius
Copper in
neutral zone
2.Bending stress with ED copper (electro-
deposited copper) on flex area
suited for static bending stress in simple installation
and maintenance conditions.
Not suited for dynamic bending stress, i.e. when the
flex area is in permanent motion!
Thermal shock test according to IPC-6013 3.10.2;
IPC-TM-650 No. 2.6.7.2
Number of cycles 100
Temperature range -55 °C to +125 °C
Time 15 min.
Thermal stress test according to IPC-6013 3.7.1;
IPC-TM-650 No. 2.6.8
solder sn60Pb40
solder temperature 288 °C ±5 °C
solder dwell time
Floating 10 sec.
on the solder
21

4.8 Controlled impedance PCBs
Controlled impedance circuits (high speed applications)
can be realized with different engineering methods
regarding layer stackup and board design.
Impedance values are strongly influenced by the dielectric
thickness as well as line width and length. Permittivity and
Microstripline - impedance calculated
lines on outer layers
5% 61%
4%
30%
copper thickness are less significant. For differential
structures (two parallel lines), the spacing between the
line tracks is critical. In addition, the thickness of the
solder mask and the permittivity of the masking material
have an effect (in so- called “micro striplines”).
Microstripline - impedance calculated
lines on inner layers
5%
4%
48%
43%
Substrate thickness Track width Permittivity Track height
In the following, four different stackup possibilities of con-trolled
impedance PCBs are shown. For unsymmetrical stack-ups
(single ended line), impedance values of approx. 50-70 Ω are
normal. For differential stackups (two parallel line tracks),
calculated impedance values amount to approx. 90-110 Ω.
Due to manufacturing tolerances, a tolerance of ± 10%
on the calculated impedance value is allowed as
technical standard.
The following drawings show the parameters which
are required for a theoretical calculation (see next
page for the legend).
Coated microstrip Edge-coupled coated microstrip
b
f
b
e2 e2
e1 eεr e1 e3eεr
d d
ε
r
ε
r
c
a a
22

Offset stripline
εr
b
εr
a
a ................ Line width (at bottom)
b ................ Line width (at top) c,
c1, c2 ... Dielectric thickness
εr .............. Dielectric permittivity
d ...............Copper thickness
e1 .............. Thickness of solder mask
on base material
Example of practical application
Edge-coupled offset stripline
εr
f
c1 b
d
c2
εr
a
e2 .............. Thickness of solder mask on line track
e3 .............. Thickness of solder mask on base material bet-
ween line tracks
eεr ............. solder mask permittivity
f ................ Line track spacing at bottom
This structure is called offset stripline. The values labeled
“soll” (= target) in the picture compare the theoretical
calculated values to actually measured values.
We shall be happy to adjust circuit design and layer stackup
to your requirements and expectations using our knowledge
and wealth of experience.
23

5 SOLDER MASK
SOLDER MASK
Mask type Probimer 65
Surface quality of solder mask Acc. to IPC sM 840 Class T (current edition)
on tracks > 10 µm
Coating thickness on base material > 30 µm
on track edges ≥ 4 µm
Mask webs between
Pad spacing ≥ 170 µm
SMD pads
standard opening SMD pad spacing ≥ 300 µm -> solder pad +100 µm circular
of solder mask -> standard solder mask web ≥ 100 µm
Minimum opening of solder mask
SMD pad spacing ≥ 170 µm -> solder pad +55 µm circular
-> minimum solder mask web ≥ 60 µm
The openings for the individual solder areas shall have the same size as the solder
Supplied data
areas themselves (zero opening). Based on the tolerances applied in printed circuit
board fabrication resulting from accuracy of fit and solder mask system, all
openings will be enlarged by a defined factor across the complete layer for CAM.
24

Excerpt from the Technical Datasheet Probimer 65
Solid content ready for use % weight 50
Physical Adhesion (cross hatch) on copper GT 0-1
properties Pencil hardness 7H - 8H
Resolution (solder dams after HAL) (with 7107) µm 50 - 60
Isopropanol > 1h
Solvent resistance
MEK > 1h
1,1,1-trichloroethane > 1h
Chemical
Methylene chloride > 1h
E'less Ni/Au passed
properties
Resistance to
E'less sn passed
organic surface
passed
passivation
Ionic contamination < 0.5 µg/cm
2
passed
Dielectric strength V/µm 150 - 170
surface resistance (initial value/IEC 167) Ω 10
14
- 10
15
Volume resistivity (initial value/IEC 93) Ω cm 10
15
- 10
16
CTI (comparative tracking index) V 200 - 0.0
Dielectric constant εr at
3.0 - 4.0
1MHz(initialvalue)
Electrical
Dielectric loss factor tanδ at
properties %
50 Hz (IEC 250)
25 °C 1.2 ± 0.1
50 °C 1.4 ± 0.1
75 °C 1.5 ± 0.1
100 °C 2.3 ± 0.1
120 °C 3.8 ± 0.1
25

Excerpt from the Technical Datasheet Probimer 65
UL 94V-0 (Underwriters Laboratories Inc.) passed
IPC-sM-840 C (Class H & T) (Trace Laboratories)
• Visual inspection
• Fungus resistance
• Hydrolytic stability
• Dielectric strength
• Dimensional stability
• Adhesion on copper
• Machinability
• Abrasion (Taber method)
passed
• Abrasion (pencil hardness)
• Curing
• Resistance to solvents and fluxes
• solderability
Approvals
• Resistance to solder
• soldering and unsoldering
• Insulation resistance
• Electro-migration
• Thermal shock testing
Internaltests
siemens sN 47044 passed
Bellcore TR-Tsy-00078 (Trace Laboratories) passed
Siemens sN 57030
passed
(E-corrosion; 21 d, 40 °C, 92% rel. hum., -> 1 x 10
8
Ω)
Siemens sN 57047 (> 5 x 10
9
Ω) passed
Bosch (24 h, 40 °C, 92% r. h., -> 5 x 10
8
Ω) passed
Philips (21 d, 40 °C, 95% r. h., 100 V -> 1 x 10
8
Ω) passed
26

5.1 Solder mask design for vias on chemical surfaces
Solder mask shall be kept away from plated through-
holes to obtain a clean, metallized defect-free hole (Fig.
1). It pre-vents liquid entry of process chemicals as well
as long-term corrosion through copper corrosion.
Covering the via with solder mask prior to surface finishing
would result in an undefined condition in the hole (Fig. 2).
Closing the hole on one side with a via filler after surface
finishing will ensure a technically faultless hole wall.
Microsection of solder
mask free via Microsection of via
covered by solder mask
Unplated copper
Mask residue in hole sleeve
Immersion tin
Fig. 1: Faultless metallized hole wall
2
Solder dam to 4
next solder pad 1
1a
Sn
Fig. A
I
m
m
e
r
s
i
o
n
Optional: Via hole filler on wave solder side
possible to avoid tin penetration
Fig. 2: Undefined hole wall
2 2
4
1 3=1
1a 1a
Fig. B
N
i
/
A
u
Fig. C
Ni/Au
I
m
m
e
r
s
i
o
n
Immersio
n
Optional: One-sided masking
possible with immersion Ni/Au
1: Final diameter 1a: Hole diameter 2: Via pad 3: Solder mask opening = final diameter
4: Solder mask opening = final diameter (1) + 0.25 mm = drill diameter (1a) + 0.10 mm
Examples of practical applications
Fig. A: Immersion tin surface Fig. B: Immersion Ni/Au sur-
face
Fig. C: Immersion Ni/Au surface,
vias covered on one side
27

6 SURFACE FINISHING
Surface Finishing
Surface Standard layer thickness
Hot-air leveling
max. 40 µm
(leaded, horizontal)
Immersion nickel/gold ≥ 3 µm nickel / 0.05 - 0.12 µm gold
Reductive gold
> 4 µm nickel / 0.4 - 0.6 µm gold
(e.g. for gold wire bonding)
Immersion tin 0.8 µm - 1.3 µm
Electro-deposited Nickel/Gold
Layer thickness acc. to Class 2 Class 3
IPC 6012 (current edition) > 3 µm Ni / > 0.8 µm Au > 3 µm Ni / > 1.25 µm Au
• Layout areas to be gold plated are interconnected to each other and beyond the board
edge via interconnecting line tracks.
Partially or fully
• on multilayer boards, interconnecting line tracks can also run through the inner layers.
• Different gold plated parts can be connected to interconnecting line tracks directly on
the printed circuit board. The tracks will be drilled off in the milling process after-
wards.
Partial gold plating with interconnecting line tracks
1
2
3
1
2
3
2 1
1
1
1
1
1 3
Electro-deposited gold
Tin, for example
1: Mill off interconnecting line tracks
2: Drill off interconnecting line tracks
3: Allow for min. spacing of 1.5 mm of gold surfaces
to adjacent tinned surfaces for masking process!
28

6.1 Partial gold plating with milled interconnecting line tracks
Example of a multilayer board. In this case, the interconnecting line tracks are routed on the inner layers.
Connecting line linked to
the gold pads through vias
Electric connection on outer layers is
realized with the plated through hole
6.2 Layout of interconnecting line tracks without solder masking
To avoid chipping when milling or faceting, the interconnecting line tracks shall always be arranged in opposite
direction to the milling direction.
Layout Milling off
Milling direction
45° Milling direction
Faceting
Ideal min. line width
is 0.3 mm
0.3 mm
Milling direction
29

7 ADDITIONAL PRINTING
Additional Printing
Spacing to
Overlapping Miscellaneous
Type other solder
of masked
areas
areas
Peters
White: SD 2692 T • Minimum ratio of letter height
Component yellow: SD 2617 ≥ 0.25 mm
-----
to line thickness: 10:1
printing HV Black: SD 2642 (10 mil) • Minimum letter height: 1.25 mm
T Datasheet: • Minimum line thickness: 0.125 mm
www.peters.de
• Maximum hole diameter:
0.55 mm (21.6 mil)
Peters • Maximum drill diameter:
Via hole SD 2361 @@ ≥ 0.25 mm
-----
0.70 mm (27.5 mil)
filling Datasheet: (10 mil) • Printed pad:
www.peters.de drill diameter + 0.2 mm
• Maximum thickness of finished pad:
50 µm
Peters
Peelable
SD
≥ 1.0 mm ≥ 1.0 mm
• Minimum printed pad (single pad):
2954 2 mm x 10 mm or 3 mm x 5 mm
solder mask (39 mil) (39 mil)
Transparent blue
Datasheet:
www.peters.de
PPI • Temperature resistant up to 300 °C
Masking tape
Type PPI 701 ≥ 1.0 mm ≥ 1.0 mm short-term
Polyimide film (39 mil) (39 mil) • Total thickness: 0.055 mm
www.ppitapes.com • Tensile strength: 50 N/cm
30

7.1 Via hole filling / plugging vias
1
2
3 3
1: Size of printed pad: hole diameter + 0.2 mm (8 mil)
2: Hole diameter
3: Spacing of printed pad to solder areas ≥ 0.25 mm (10 mil)
Microsection of via with hole filler
Max. thickness of finished printed pad is 50 µm
7.2 Peelable solder mask or masking tape
2 3
1
1
1
1: Areas to be masked
3 2
2: Overlapping of mask area ≥ 1.0 mm
3: Spacing of peel-off masking edge to solder areas ≥ 1.0 mm
31

8 MECHANICAL MANUFACTURING
8.1 Drilling
Drilling
Min. drilled diameter 0.25 mm; aspect ratio 1:8 (drill diameter:board thickness)
Max. drilled diameter Up to 6.35 mm in 0.05 mm increments
Tolerance of plated through-holes 0.15 mm (e.g. -0.05 / +0.1 mm)
Tolerance of non-plated through-
0.10 mm (e.g. -0 / +0.1 mm)
holes
Max. diameter of plated through- 7.0 mm (for larger holes, refer to drawing Alternative for large plated through-
holes holes)
Thermal vias
When fabricating many holes in a confined space, a material
spacing of 300 µm shall be allowed for between the holes.
≥300 µm
1
2
3
1:Final diameter
2:Hole diameter
3:Copper layer incl. surface finishing
Alternative for large plated through-holes
NPT hole
Several plated through holes
arranged on the annular ring!
Application example:
32

8.1.1 Mechanical blind holes
A special drill bit is used to create blind holes across several Etched microsection
layers in multilayer boards. The tapered shape of this drill bit
requires the following pad diameters in relation to the drilling
depth.
Due to their greater volume, these blind holes cannot be
positioned in solder pads.
Blind hole Copper plating thickness according to IPC-6012
Aspect ratio max. 1:0.8
L1 Hole type
Requirements
Class 2 Class 3
L2
Copper plating of 20 µm mean val. 25µm mean val.
through-hole 18 µm min. value 20µm min. value
L3
Copper plating of 20 µm mean val. 25µm mean val.
blind hole 18 µm minimum 20µm min. value
selecting the appropriate pad diameter (schematic representation)
Ideal pad diameter 600 µm
Hole depth max. 400 µm
300µm
200µm
100µm
0µm
120 µm
Note: The pad size for drilled blind holes depends on the hole depth!
For intermediate dimensions, use the next higher level.
FR4 / core Copper Minimum pad diameter
Min. pad
diameter
min. 500 µm
min. 400 µm
min. 350 µm
33

8.2 Milling
Milling
Cutter width (ø in mm) 0.8; 1.0; 1.2; 1.4; 1.6; 2.0; 2.4; 3.0
Spacing between the boards on the multiple printed
10 mm in both directions
panel
≤ 200 mm ± 0.1 mm
Tolerance of length/width > 200 mm ≤ 300 mm ± 0.15 mm
> 300 mm ± 0.2 mm
Tolerance of hole pattern to milled outline ± 0.2 mm
Tolerance of wire routing to milled outline ± 0.2 mm
Copper set back from edge min. 0.3 mm
Tolerance of depth milling (cf. sketches) ± 0.1 mm or ± 0.15 mm resp.
Depth milling
Reference is depth Reference is remaining material
Tolerance ± 0.10 mm Tolerance ± 0.15 mm
Example of milled edge
34

8.3 scoring
SCORING
Spacing between the boards on the
0 mm in both directions
multiple printed panel
Positioning accuracy ± 0.1 mm
Tolerance of length/width -0 / +0.25 mm for 0.3 mm remaining web of scoring
Copper set back from edge for material
min. 0.6 mm
thickness up to 1.6 mm
Copper set back from edge for material
min. 0.7 mm
thicker than 1.6 mm
Minimum route length for jump
20 mm
scoring
score ending 10 mm
Tolerances
Remaining web 0.3 mm Score line offset top Center offset
to bottom side
15°
Tolerance ± 0.10 mm Tolerance ± 0.10 mm Tolerance ± 0.10 mm
Example of scored edge
35

8.4 Chamfering gold ridges
FACETING
Board thickness Facet angle (1) Facet depth (2) Gold contacts set back from edge (3)
≤ 1.00 mm 45° 0.30 mm ± 0.15 mm 0.60 mm ± 0.10 mm
1.20 mm 45° 0.40 mm ± 0.15 mm 0.70 mm ± 0.10 mm
≥ 1.60 mm 45° 0.50 mm ± 0.15 mm 0.80 mm ± 0.10 mm
≤ 1.00 mm 30° 0.50 mm ± 0.15 mm 0.80 mm ± 0.10 mm
1.20 mm 30° 0.70 mm ± 0.15 mm 1.00 mm ± 0.10 mm
≥ 1.60 mm 30° 0.80 mm ± 0.15 mm 1.10 mm ± 0.10 mm
≤ 1.00 mm 15° 0.70 mm ± 0.15 mm 1.00 mm ± 0.10 mm
1.20 mm 15° 0.80 mm ± 0.15 mm 1.10 mm ± 0.10 mm
≥ 1.60 mm 15° 0.90 mm ± 0.15 mm 1.20 mm ± 0.10 mm
For printed circuit board fabricating, the gold ridges are set back by the value for (3) in relation to board
thickness and facet angle.
Allow for min. spacing of 1.5 mm of gold surfaces to adjacent tinned surfaces for masking process.
3
2
1
Copper (Cu) Nickel (Ni) Gold(Au) Board edge
3: Setting back of gold edge to avoid that the tool touches
the copper or gold when chamfering the basic material to
prevent short circuits between the gold contacts.
A solder mask web is arranged in front
of the gold pads to avoid chipping
(and hence short circuits) when faceting.
36

8.5 ZIF connectors (Zero Insertion Force) for rigid-flex boards
Printed circuit board manufacturers face the technical challenge of mastering the tolerance of the lateral spacing of the
mating surfaces to the connector outline in combination with a final thickness of 0.3 mm with a tolerance of ± 0.05 mm.
Technical drawing of ZIF connector
Applicable FPC Dimensions
B ±0.07
0.5
C ±0.05
±0.03
0.5 ±0.1
0.35±0.03
2.8
5
(Reinforcement
board)
T=0.3 ±0.05 (Conductive plating)
Tolerance controlled depth milling for ZIF connectors
0.30 mm
± 0.05 mm
Controlled depth milling
Solder mask Epoxyadhesive Copper Polyimide FR4 core
37

Current-carrying capacity
The stackup of layers is decisive for the current-
carrying capacity of a copper wire. Its current-carrying
capacity, for example, doubles if two massive inner
layers without intrinsic heating are positioned below.
The geometrical design is also decisive. A wire of 0.5
x 2.0 mm, e.g., can carry higher
current than a wire of 1.0 x 1.0 mm, both having the
same cross-sectional size.
The reason is the larger surface of the 0.5 x 2.0 mm
wire resulting in a better heat dissipation through the
surrounding board material (FR4, solder mask, etc.).
Low heat dissipation High heat dissipation
35 µm
stackup
1.6 mm
35 µm
0,5 mm
Rd. wire Cu profile Cu profile Cu profile Cu profile Rd. wire Cu profile Cu profile Cu profile Cu profile
0.5 mm 2x0.5 mm 4x0.5 mm 8x0.5 mm 12x0.5 mm 0.5 mm 2x0.5 mm 4x0.5 mm 8x0.5 mm 12x0.5mm
Delta T [°C] Ampere Ampere Ampere Ampere Ampere Ampere Ampere Ampere Ampere Ampere
10 3.26 10.41 17.21 28.45 38.17 5.90 18.84 31.13 51.46 69.05
20 4.61 14.73 24.34 40.23 53.98 8.34 26.64 44.03 72.78 97.65
30 5.64 18.03 29.81 49.27 66.11 10.21 32.63 53.93 89.14 119.60
40 6.52 20.82 34.42 56.89 76.34 11.79 37.67 62.27 102.93 138.10
50 7.29 23.28 38.48 63.61 85.35 13.18 42.12 69.62 115.07 154.40
60 7.98 25.50 42.16 69.68 93.49 14.44 46.14 76.26 126.06 169.14
70 8.62 27.55 45.53 75.26 100.98 15.60 49.84 82.38 136.16 182.69
80 9.22 29.45 48.68 80.46 107.96 16.67 53.28 88.06 145.56 195.30
90 9.78 31.24 51.63 85.34 114.51 17.69 56.51 93.40 154.39 207.15
100 10.30 32.93 54.42 89.96 120.70 18.64 59.57 98.46 162.74 218.35
110 10.81 34.53 57.08 94.35 126.59 19.55 62.47 103.26 170.68 229.01
120 11.29 36.07 59.62 98.54 132.22 20.42 65.25 107.85 178.27 239.19
Reliability
- DIN EN 60068-2-14: Change of temperature test,
1,000 cycles, -40 °C to +155 °C
-JEDEC A101-A: Temperature humidity bias
life test, storage at 85 °C/85 % rel. hum.,
1,000 hrs.
38

9 PACKAGING METHODS
To grant the highest quality of the PCBs, humidity should be kept under control both during storage and
shipping. Therefore, PCBs shall be packaged under vacuum, including desiccant material and a humidity
indicator card (HIC). PCBs shall be packaged in a barrier material that meets the requirements of IPC-
1601/JEDEC J-STD-033.
Please apply the following updated rules to all the goods shipped, by every shipping method (air, sea,
ground etc), both for fast productions/sampling and mass productions, must follow this packaging guidelines
otherwise it will not be accepted, leading to a non conformity.
1) All PCBs or panels will have to be packaged inside a vacuum bag, materials shall meet the J-STD-
033 requirements, such as:
1. Nylon/ Foil/ Polyethylene - outer layer of ESD nylon, aluminum foil middle layer and an inner layer of
polyethylene – Example material is 3M Dri-Shield Moisture Barrier 3400.
2. Tyvek / Foil / Polyethylene – Outer layer of Tyvek with aluminum foil middle layer and an inner layer of
polyethylene.
3. Aluminized Polyester / polyethylene - acceptable material when used with the proper thickness material.
Material thickness > 0.18mm (0.007 in) thick.
The bag shall be heat sealed to keep out moisture. Leave enough excess material to allow for a minimum of
(1) resealing of the moisture barrier bag to facilitate incoming inspection.
Full air evacuation is not required or recommended as excessive air evacuation can impede the barrier
performance of the packaging material due to punctures and can also degrade the effectiveness of the
desiccant. Full air evacuation may be used when boards are shipped as loose pieces to avoid damage from
shifting and abrasion;
2) Desiccant material, such as silica gel, and humidity indicator (HIC) must be included in every bag.
Desiccant material quantity and quality used in the internal packaging shall be in accordance with IPC-
1601/JEDEC J-STD-033 and shall be sulfur free.
The desiccant materials shall be placed on the edges of the PCB, to avoid potential board warping if
packages are stacked within the shipping carton. This placement also will prevent any interaction between
the desiccant and the soldering finish surfaces.
The HIC shall be packaged inside the outer moisture barrier bag along with the desiccant.
The HIC will serve as an aid in determining the exposure to moisture to which the PCBs have been subject
during storage and shipping. Please refer to the image below:
3) A sticker listing part number, data code and number of PCBs included must be labeled on the bag,
please refer to the sample picture below;
39

Part Number
Quantity (pcs.)
Data Code
Notes
4) If previously agreed with Tekube, when the shipping includes panels with x-out or some reworked
boards (on solder mask, on copper side etc. etc.), these goods will have to be clearly identifiable, packaged in
a separate box and marked on the outside of the box;
5) The box must also be labelled on the outside (on two sides in case one label gets unreadable) using
the same label of point 3 above;
6) The box has to be filled up in order to avoid vacuum bag moving, colliding while being handled and
shipped;
7) Polystyrene and cardboard paper are not allowed to fill up the boxes;
8) A maximum of 25 panels can be packaged inside a vacuum Bag. In the special case of PCB with
peelable mask needs, the limit is lowered to 15 panels per vacuum bag;
9) All the boxes must be made up of 3 layers cardboard, if this is not possible, supplier must to notify
TEKUBE quality department before shipping;
10) Only for Aluminum PCBs, upon special request from customer, vacuum bag must to contain paper-
sheet between the PCBs and/or wood panels, on both sides, to grant more rigidity;
11) When multiple boxes are shipped, particularly on a pallet, a maximum of 5 (five) boxes can be piled up
to avoid deformation of the boxes and potential damages to the goods.
40

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