The document describes the characteristics and fabrication process of epitaxial devices such as diodes and transistors. It discusses the depletion region in p-n junctions and how epitaxial structures can achieve low capacitance, high breakdown voltage, and low series resistance. The fabrication steps for planar epitaxial diodes and transistors are outlined, including starting with an n/n+ epitaxial wafer and diffusing p-type and n-type regions. Bipolar IC manufacturing involves growing an epitaxial layer, isolation diffusion, base diffusion, emitter diffusion, contact masking, and metallization.

1. EPITAXIAL DEVICES – CHARACTERISTICS
• Junction Characteristics:-
• A reverse-biased p-n junction can be considered to be a parallel-plate capacitor with the
depletion region being the insulator or dielectric as shown in the figure below.
• The depletion or space-charge region is the region adjacent to the p-n junction that is
essentially depleted (or devoid) of all mobile charges (that is, free electrons and holes), so
that it acts like an insulator.
• For almost all diffused p-n junctions the doping on the diffused layer side of the
junction will be very much heavier than the doping on the other (substrate) side of the
junction, so that most diffused junctions can be considered to be one-sided junctions.

2. (A) CORRESPONDS TO A GENERAL CASE OF P-N JUNCTION, WHILE FIGURE (B)
CORRESPONDS TO A ONE-SIDED P-N JUNCTION.

3. EPITAXIAL STRUCTURES:-
• For low junction capacitance Cj, low doping, that is, lightly doped substrate, is
required.
• For high breakdown voltage, low doping, that is, lightly doped substrate, is
required.
• For low series resistance, Rs, heavy doping, that is, low resistivity substrate is
required.
• The epitaxial structure shown in the figure below, offers a good way of resolving
this conflict and simultaneously satisfying the capacitance, breakdown voltage
and series resistance requirements.
• As long as the depletion region remains entirely within the lightly doped epitaxial
layer and does not reach the heavily doped n+ substrate
• the capacitance and breakdown voltage will be a function only of the epitaxial

5. PLANAR EPITAXIAL DIODE FABRICATION
STEPS • the fabrication steps for the epitaxial planar diode are as follows.
• The starting material is n/n+ epitaxial wafer with a 0.005-ohm-cm (Sb-doped} substrate
and an epitaxial layer of anywhere from 5 to 25 micro meters thick and phosphorus
doped to resistivities in the range 5 to 50-ohm-cm.
• An oxide layer about 5000 to 8000A thick is grown.
• Using first photolithography windows are opened in the oxide layer for the P+ diffusion.
• A p+ diffused layer about 1 to 3 micro meters thick is produced to be the anode region of
the diode.
• Using second photolithography anode contact windows are produced.
• Anode contacts are produced using aluminium deposition carried out by metallization
process

6. • Using third photolithography the metallization is patterned for anode contacts.
• The metallization film is sintered or alloyed to form a good mechanical bond to
the silicon and to produce a low- resistance, non rectifying ohmic contact.
• Sintering or alloying is a heat treatment at about 500 to 600°C.
• A back-side metallization is carried out. In this, a thin film of gold is evaporated
on to the lapped back side of the wafers.
• This is for the eutectic die (chip) bonding of the chips to gold-plated headers or
substrates at temperatures in the range 400° to 420°C, the gold/silicon eutectic
temperature being 370°C.

7. PLANAR EPITAXIAL
TRANSISTOR:-
The processing steps are as follows:--
• The starting material is n/n+ epitaxial wafer with 0.005
ohm-cm Sb-doped substrate and n-type epitaxial layer of
about 6 to 12 micro meters thickness and 0.3 to 3 ohm-
cm resistivity.
• An oxide layer of about 5000 to 8000A thickness is
grown.
• Using first photolithography, oxide windows arc etched
for the base diffusion.
• A two-step deposition-drive in boron diffusion is
performed for base region. The junction depth is about 2
to 3 micro meters. Sheet resistance is of about 200 ohm
per square.
• The drive-in diffusion is performed in an oxidizing

8. • Using second photolithography, oxide windows are etched for the emitter
diffusion.
• A high surface concentration phosphorus diffusion is performed to produce an
n+ diffused layer emitter region with a junction depth of about 2 to 2.5 micro
meters.
• Using third photolithography, oxide windows are etched for emitter and base
contacts.
• An aluminium thin film of about 0.5 to 1 micro meter separate thickness is
deposited on the front surface of the surface using metallization process.
• Using fourth photolithography, windows are etched for emitter and base
contact areas.
• Heat treatment at 500 to 600°C for sintering or alloying the metallization film is
carried out.

9. TRIPLE DIFFUSED
PLANAR
TRANSISTOR:-
• In a triple diffused transistor as shown
in the figure below, the collector region
is formed by an n-type diffusion into
the p-type wafer.
• The drawbacks of this structure are that
the series collector resistance is high
and the collector-to-emitter breakdown
voltage is low.

10. • The former occurs because the impurity concentration in the portion of
the collector diffusion below the collector-to-base junction is low giving
the region high resistivity.
• The latter occurs because near the surface of the collector the
concentration of impurities is relatively high, resulting in a low breakdown
voltage between the collector and base diffusions.
• Thus the concentration profile provided by the diffused collector is very
disadvantageous; what is required is a low impurity concentration at the
collector-base junction for high breakdown voltage and a high
concentration below the junction for low collector resistance.

11. N-CHANNEL JEET
FABRICATION STEPS
• The processing sequence for the
device follows :-
• The starting material is n/p epitaxial
wafer.
• Thermal oxidation is carried out
• Using first photolithography,
windows are opened for p+ boron
top gate diffusion.

12. • Boron diffusion for gate region is carried out.
• Using second photolithography windows are opened for n+ source and drain
diffusion.
• n+ phosphorus diffusion is carried out to produce the source and drain regions
of the JFET. Using third photolithography, contact windows are opened
• Metallization is carried out.
• Using fourth photolithography metallization patterning for source, drain, and
gale contact areas is carried out
• Contact sintering or alloying is done.
• Back-side metallization is carried out.

13. BIPOLAR IC MANUFACTURING PROCESS:--

18. P-N JUNCTION ISOLATION:-
1. One begins with the p-type substrate on which n-epitaxial layer is grown. If
the component to be fabricated is transistor, then buried layer have to be
formed before growing epi-layer. Figure [a] shows epi-layer growth over
substrate without buried layer. The epi-layer is then covered with SiO2 layer.
2. A p-type diffusion is now performed from the surface of the wafer. Since this
is to be performed in selected areas, an isolation mask is prepared prior to this
diffusion. A long drive-in time is required for p-type diffusion so that the
acceptor concentration is greater than the epi-layer donor concentration
throughout the region of epi-layer.

20. • Thus the portion of wafer at the location of isolation diffusion is changed to
p-type from the surface of wafer to the substrate. This is shown in the figure
[b].
• In other words, the substrate is extended toward the surface and acts as an
isolation wall.
• This isolation wall causes the formation of p-n junction everywhere around
the n-type islands except at the surface.
• If the substrate is connected to a voltage which is more negative than any
of the n-region voltages, the diodes shown will be reversed biased and
negligible current will flow.
• Thus isolation is achieved since any reverse biased p-n junction is associated
with a depletion capacitance; this will have parasitic effect associated with
junction, particularly, at high frequencies.

21. DISADVANTAGE OF P-N JUNCTION
ISOLATIONS
1.The time required for such isolation technique is considerably longer due to
diffusion time taken, which is longer than any of other diffusions.
2.Lateral diffusion is significant due to longer time taken by isolation diffusion,
hence considerable clearance must be used for isolation regions.
3.Isolation diffusion takes an area of the wafer surface which is significant
portion of the chip area. From component density consideration, this area is
wasted.
4.P-N junction isolation method introduces significant parasitic capacitance
which degrades circuit performance. The parasitic capacitance is introduced
by isolation sidewall and bottom epitaxial substrate junction.

22. CONSTRUCTION OF A MONOLITHIC
BIPOLAR TRANSISTOR--
The fabrication of a monolithic transistor includes the following steps
1. Epitaxial growth. 2. Oxidation
3. Photolithography 4. Isolation diffusion
5. Base diffusion 6. Emitter diffusion
7. Contact mask 8. Aluminium metallization
9. Passivation

23. 1. EPITAXIAL
GROWTH:-
• an epitaxial layer of lightly
doped N-silicon is grown on the
P-type substrate by placing the
wafer in the furnace at 12000 C
and introducing a gas
containing phosphorus (donor
impurity).

24. 2. OXIDATION:--

25. PHOTOLITHOGRAPHY:--
the surface of the oxide is first covered
with a thin uniform layer of
photosensitive emulsion (Photo resist).
The mask, a black and white negative of
the requied pattern, is placed over the
structure exposed to ultraviolet light, the
photo resist under the transparent region
of the mask becomes poly-merized.
The mask is then removed and the
wafer is treated chemically that removes
the unexposed portions of the
photoresist film

26. 4. ISOLATION DIFFUSION:-
The most important techniques for isolation are:
1. PN junction Isolation
2. Dielectric Isolation

27. 1. PN JUNCTION ISOLATION
• In PN junction isolation technique, the P+ type impurities are selectively
diffused into the N-type epitaxial layer so that it touches the P-type
substrate at the bottom.
• This method generated N-type isolation regions surrounded by P-type
moats.
• If the P-substrate is held at the most negative potential, the diodes will
become reverse-biased, thus providing isolation between these islands.

28. 2. DIELECTRIC ISOLATION:-
• In dielectric isolation method, a layer of solid dielectric such as
silicon dioxide or ruby surrounds each component and this dielectric
provides isolation.
• The isolation is both physical and electrical.
• This method is very expensive due to additional processing steps
needed and this is mostly used for fabricating IC‘s required for
special application in military and aerospace

29. 5.BASE DIFFUSION:--
• Formation of the base is a critical step in the construction of a bipolar
transistor.
• The base must be aligned, so that, during diffusion, it does not come into
contact with either the isolation region or the buried layer.
• Frequently, the base diffusion step is also used in parallel to fabricate
diffused resistors for the circuit.
• The value of these resistors depends on the diffusion conditions and the
width of the opening made during etching.

30. 6. EMITTER DIFFUSION:--
•Emitter Diffusion is the final step in the fabrication of the
transistor.
•The emitter opening must lie wholly within the base.
• Emitter masking not only opens windows for the emitter,
but also for the contact point, which provides a low
resistivity ohmic contact path for the emitter terminal.

31. 7. CONTACT MASK:--
• After the fabrication of emitter, windows are etched into the N-type regions
where contacts are to be made for collector and emitter terminals.
• Heavily concentrated phosphorus N+ dopant is diffused into these regions
simultaneously.
• The reasons for the use of heavy N+ diffusion is explained as Aluminium,
being a good conductor used for interconnection, is a P-type of impurity
when used with silicon.

32. 9. PASSIVATION/ ASSEMBLY AND
PACKAGING:--
• Metallization is followed by passivation, in which an insulating and protective
layer is deposited over the whole device.
• This protects it against mechanical and chemical damage during subsequent
processing steps.
• Doped or undoped silicon oxide or silicon nitride, or some combination of them,
are usually chosen for passivation of layers.