I – SEMESTER                            CMOS VLSI DESIGN  Subject Code                  : 12EC021             IA Marks    ...
sharing, Clocking- clock generation, clock distribution, clocked storageelements. (Ref.2 Chap.7)Reference Books:     1. Ne...
technological library with given Constraints*. Do the initial timingverification with gate level simulation.              ...
e. Verify & Optimize for Time, Power and Area to the given   constraint***2. Design the following circuits with given spec...
* Appropriate specification should be given.** Applicable Library should be added & information should be given tothe Desi...
reduction, design effort reduction, performance maximization. (Ref.2 Chap.2,Ref .6 Chap-3.5, publication-3,5)System On Chi...
4. Michael Keating, Pierre Bricaud, “Reuse Methodology manual for        System on chip designs”, Kluwer academic Publishe...
The Embedded System Development Environment: The IntegratedDevelopment Environment (IDE), Types of Files Generated on Cros...
i.The main thread creates a child thread with default stack size and          name ‘Child_Thread’.          ii.The main th...
based verification techniques that were developed in the past are consideredinadequate to-day, since they require too many...
Static Timing Verification. Concept of static timing analysis. Cross talk andnoise. Limitations of STA. slew of a waveform...
ELECTIVE – I             DIGITAL SYSTEM DESIGN USING VERILOG Subject Code                   : 12EC121               IA Mar...
NANOELECTRONICS Subject Code                   : 12EC054                IA Marks        : 50 No. of Lecture Hours /week   ...
confined stark effect,nonlinear effects,coherence and dephasing,characterization of semiconductor nanostructures:optical e...
Introduction: Full Custom with ASIC, Semi custom ASICS, Standard Cellbased ASIC, Gate array based ASIC, Channeled gate arr...
II – SEMESTER      DESIGN OF ANALOG & MIXED MODE VLSI CIRCUITS Subject Code                  : 12EC025              IA Mar...
Bandgap Reference & Switched Capacitor Circuits: GeneralConsiderations, Supply Independent biasing, Temperature independen...
i) DC Analysis            ii). AC Analysis            iii) Transient Analysis   b. Draw the Layout and verify the DRC, ERC...
Multi-resource Services:Blocking, Deadlock and livestock, Critical sections to protect sharedresources, priority inversion...
(Reference Book 3 can be used to give Lab. Assignments)USE LINUX/SOLARIS/QNX OS ONLY.1. Implement simple IPC protocol.2. I...
Server’. The 2nd process reads the data written by the pipe server to the pipeand displays it on the console. Use event ob...
provide some digital signal processing capability to further reduce thesystem cost.Power dissipation is often a considerat...
LOW POWER VLSI DESIGN Subject Code                   : 12EC047                 IA Marks        : 50 No. of Lecture Hours /...
REFERENCE BOOKS:    1.Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit        Design” Wiley, 2000    2.Gary K. Yea...
Special Purpose Subsystems: Packaging, power distribution, I/O, Clock,Transconductance amplifier, follower integrated circ...
Placement, Floor Planning & Pin Assignment: problem formulation,simulation base placement algorithms, other placement algo...
applications in communication systems and signal processing. It is intendedto introduce a basic course in multirate signal...
III – SEMESTER                      CMOS RF CIRCUIT DESIGN Subject Code                   : 12EC020                 IA Mar...
REFERENCE BOOKS:    1.B. Razavi, “RF Microelectronics” PHI 1998    2.R. Jacob Baker, H.W. Li, D.E. Boyce “CMOS Circuit Des...
Multiple Level Combinational Optimizations: Models and transformationsfor combinational networks, algebraic model, Synthes...
Random signals, Discrete Random fields, Spectral density function.(Ref.1,Chap.2)Image Perception: Light, Luminance, Bright...
H.263, MPEG I, MPEG 2, MPEG 4, MPEG 7 and beyond, Content basedvideo indexing. (Ref.4)Reference Books:1. K. Jain, “Fundame...
Electronic Engine Control – Engine parameters, variables, EnginePerformance terms, Electronic Fuel Control System, Electro...
simple circuit phasor domain, RF impedance matching, properties of waves,transmission media, micro strip lines, high frequ...
MESFETS: MESFET and MODFET operations, quantitative description ofMESFETS.MIS Structures and MOSFETS: MIS systems in equil...
RF MEMS Subject Code                  : 12EC127               IA Marks      : 50 No. of Lecture Hours /week    : 04       ...
3.“Transaction Level Modeling with System C”. TLM Concepts andApplications for Embedded Systems, by Frank Ghenassia,Spring...
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  1. 1. I – SEMESTER CMOS VLSI DESIGN Subject Code : 12EC021 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100MOS Transistor Theory: n MOS / p MOS transistor, threshold voltageequation, body effect, MOS device design equation, sub threshold region,Channel length modulation. mobility variation, Tunneling, punch through,hot electron effect MOS models, small signal AC Characteristics, CMOSinverter, βn / βp ratio, noise margin, static load MOS inverters, differentialinverter, transmission gate, tristate inverter, BiCMOS inverter. (Ref.1Chap.2) CMOS Process Technology: Lambda Based Design rules, scaling factor,semiconductor Technology overview, basic CMOS technology, p well / nwell / twin well process. Current CMOS enhancement (oxide isolation, LDD.refractory gate, multilayer inter connect), Circuit elements, resistor, capacitor,interconnects, sheet resistance & standard unit capacitance concepts delayunit time, inverter delays, driving capacitive loads, propagate delays, MOSmask layer, stick diagram, design rules and layout, symbolic diagram, maskfeints, scaling of MOS circuits. (Ref.3 Chap.4, 5) Basics of Digital CMOS Design: Combinational MOS Logic circuits-Introduction, CMOS logic circuits with a MOS load, CMOS logic circuits,complex logic circuits, Transmission Gate. Sequential MOS logic Circuits -Introduction, Behavior of hi stable elements, SR latch Circuit, clocked latchand Flip Flop Circuits, CMOS D latch and triggered Flip Flop. DynamicLogic Circuits - Introduction, principles of pass transistor circuits, Voltageboot strapping synchronous dynamic circuits techniques, Dynamic CMOScircuit techniques. (Ref.4 Chap.7, 8, 9) CMOS Analog Design: Introduction, Single Amplifier. DifferentialAmplifier, Current mirrors, Band gap references, basis of cross operationalamplifier. (Ref.5 Chap.3.2, 4.2, 5.1 )Dynamic CMOS and clocking: Introduction, advantages of CMOS overNMOS, CMOSSOS technology, CMOSbulk technology, latch up in bulkCMOS., static CMOS design, Domino CMOS structure and design, Charge 1
  2. 2. sharing, Clocking- clock generation, clock distribution, clocked storageelements. (Ref.2 Chap.7)Reference Books: 1. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: nd A System Perspective,” 2 edition, Pearson Education (Asia) Pvt.. Ltd., 2000. 2. Wayne, Wolf, “Modern VLSI design: System on Silicon” nd Pearson Education”, 2 Edition 3. Douglas A Pucknell & Kamran Eshragian , “Basic VLSI Design” rd PHI 3 Edition (original Edition – 1994) 4. Sung Mo Kang & Yosuf Lederabic Law, “CMOS Digital Integrated Circuits: Analysis and Design”, McGraw-Hill (Third Edition) 5. “Design of Analog CMOS Integrated Circuits”, Behzad Razavi, TMH, 2007.-----------------------------------------------------------LABORATORY EXPERIMENTS CMOS VLSI DESIGN LAB: (Use any of the EDA Tools) DIGITAL DESIGNASIC-DIGITAL DESIGN FLOW1. Write Verilog Code for the following circuits and their Test Bench forverification, observe the waveform and synthesize the code with 2
  3. 3. technological library with given Constraints*. Do the initial timingverification with gate level simulation. 1.An inverter 2.A Buffer 3.Transmission Gate 4.Basic/universal gates 5.Flip flop -RS, D, JK, MS, T 6.Serial & Parallel adder 7.4-bit counter [Synchronous & Asynchronous counter] 8.Successive approximation register [SAR] •An appropriate constraint should be given 1.Using SPICE how do you measure the power for a digital circuit. 2.Using a suitable simulator determine the logic propagation delay available in a cycle for a traditional domino pipeline using 500 ps clock cycle. Assume there is zero clock skew. 3.Simulate the worst-case propagation delay of an 8-bit dynamic NOR gate driving a fanout of 4. 4.Simulate a pseudo –nMOS inverter in which the pMOS transistor is half the width of the nMOS transistor. What are the rising, falling and average logical efforts? What is Vol? 5.Simulate a static CMOS circuit to compute f = (A+B)(C+D) with least delay. Each input can present a maximum of 30 lambda of transistor width. The output must drive a load equivalent to 500 lambda of transistor width. Choose transistor size to achieve least delay and estimate the this delay in t. PART - B ANALOG DESIGNAnalog Design Flow1. Design an Inverter with given specifications*, completing the design flowmentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design 3
  4. 4. e. Verify & Optimize for Time, Power and Area to the given constraint***2. Design the following circuits with given specifications*, completing thedesign flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. i) A Single Stage differential amplifier ii) Common source and Common Drain amplifier.3. Design an op-amp with given specification* using given differentialamplifier Common source and Common Drain amplifier in library** andcompleting the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii). AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design.4. Design a 4 bit R-2R based DAC for the given specification andcompleting the design flow mentioned using given op-amp in the library**. a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design.5. For the SAR based ADC mentioned in the figure below draw the mixedsignal schematic and verify the functionality by completing ASIC DesignFLOW. [Specifications to GDS-II] 4
  5. 5. * Appropriate specification should be given.** Applicable Library should be added & information should be given tothe Designer.*** An appropriate constraint should be given6 Design a simple 8-bit ADC converter using any one of the tools givenabove.7. Design a simple NAND/NOR gate using any one of the tools given above.(Any other experiments may be added in supportive of the course)-------------------------------------------------------------------------- SoC Design Subject Code : 12EC129 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Goal of the course – Today, VLSI chips are entire “system-on-chip” designs,which include processors, memories, peripheral controllers, and connectivitysub-systems. The course aims to provide an appreciation for the motivationbehind SoC design, the challenges of SoC design, and the overall SoC designflow. Motivation for SoC Design - Review of Moore’s law and CMOS Scaling,benefits of system-on-chip integration in terms of cost, power, andperformance. Comparison on System-on-Board, System-on-Chip, andSystem-in-Package. Typical goals in SoC design – cost reduction, power 5
  6. 6. reduction, design effort reduction, performance maximization. (Ref.2 Chap.2,Ref .6 Chap-3.5, publication-3,5)System On Chip Design Process:A canonical SoC Design, SoC Designflow waterfall vs spiral, top down vs Bottom up. Specification requirement,Types of Specification , System Design process, System level design issues,Soft IP Vs Hard IP, IP verification and integration, hardware-softwarecodesign, Design for timing closure, Logic design issues Verificationstrategy, On chip buses and interfaces, Low Power, Hardware Accelerators inan SOC. (Ref -4, chap-2,3 Publication-1,5) Embedded Memories –cache memories, flash memories, embeddedDRAM, Topics related to cache memories. Cache coherence. MESI protocoland Directory-based coherence. (Ref -3, chap: 10.5, Ref -6, chap 10) Interconnect architectures for SoC. Bus architecture and its limitations.Network on Chip (NOC) topologies. Mesh-based NoC. Routing in an NoC.Packet switching and wormhole routing. (Ref -1, chap-12).MPSoCs: What,Why,How MPSoCs. Techniques for designing MPSoCs,Performance and flexibility for MPSoCs design, (Ref -5, Chap-1, 2, 5,Publication-4)Case study: A Low Power Open Multimedia Application Platform for 3GWireless (Publication-6)Reference Books: 1. Sudeep Pasricha and Nikil Dutt,”On-Chip Communication Architectures: System on Chip Interconnect”, Morgan Kaufmann Publishers © 2008 2. Rao R. Tummala, Madhavan Swaminathan, “Introduction to system on package sop-Miniaturization of the Entire System”, McGraw- Hill-2008. 3. James K. Peckol, “Embedded Systems: A Contemporary Design Tool”, WILEY Student Edition. 6
  7. 7. 4. Michael Keating, Pierre Bricaud, “Reuse Methodology manual for System on chip designs”, Kluwer academic Publishers, 2nd edition- 2008. 5. Ahmed Amine Jeraya, Wayne Wolf, “Multiprocessor System On chip”, Morgan Kauffmann, 2005. 6. Sung- Mo Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits”, Tata Mcgraw-hill, 3rd Edition. ADVANCED EMBEDDED SYSTEMS Subject Code : 12EC118 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Typical Embedded System : Core of the Embedded System, Memory,Sensors and Actuators, Communication Interface, Embedded Firmware,Other System Components.Characteristics and Quality Attributes of Embedded Systems:Hardware Software Co-Design and Program Modelling: FundamentalIssues in Hardware Software Co-Design, Computational Models inEmbedded Design, Introduction to Unified Modelling Language,Hardware Software Trade-offs.Embedded Hardware Design and Development :EDA Tools, How to UseEDA Tool, Schematic Design – Place wire, Bus , port, junction, creatingpart numbers,Design Rules check, Bill of materials, Netlist creation ,PCB Layout Design – Building blocks, Component placement, PCBtrack routing.Embedded Firmware Design and Development: Embedded FirmwareDesign Approaches, Embedded Firmware Development LanguagesReal-Time Operating System (RTOS) based Embedded System Design:Operating System Basics, Types of OS, Tasks, Process and Threads,Multiprocessing and Multitasking, Task Scheduling, Threads, Processes andScheduling: Putting them altogether, Task Communication, TaskSynchronization, Device Drivers, How to Choose an RTOS 7
  8. 8. The Embedded System Development Environment: The IntegratedDevelopment Environment (IDE), Types of Files Generated on Cross-compilation, Disassembler/Decompiler, Simulators, Emulators andDebugging, Target Hardware Debugging, Boundary Scan.REFERENCE BOOKS: 1.Introduction to Embedded Systems, Shibu K V, Tata McGraw Hill Education Private Limited, 2009 2.Embedded Systems – A contemporary Design Tool, James K Peckol, John Weily, 2008.Lab Experiments:I. Advanced Embedded Systems1.Use any EDA (Electronic Design Automation) tool to learn the EmbeddedHardware Design and for PCB design.2.Familiarize the different entities for the circuit diagram design.3.Familiarize with the layout design tool, building blocks, componentplacement, routings, design rule checking etc.II. Embedded Programming Concepts (RTOS)1.Create ‘n’ number of child threads. Each thread prints the message “ I’m inthread number …” and sleeps for 50 ms and then quits. The main threadwaits for complete execution of all the child threads and then quits. Compileand execute in Linux.2.Implement the multithread application satisfying the following : i.Two child threads are crated with normal priority. ii.Thread 1 receives and prints its priority and sleeps for 50ms and then quits. iii.Thread 2 prints the priority of the thread 1 and rises its priority to above normal and retrieves the new priority of thread 1, prints it and then quits. iv.The main thread waits for the child thread to complete its job and quits.3.Implement the usage of anonymous pipe with 512 bytes for data sharingbetween parent and child processes using handle inheritance mechanism.4.Test the program below using multithread application- 8
  9. 9. i.The main thread creates a child thread with default stack size and name ‘Child_Thread’. ii.The main thread sends user defined messages and the message ‘WM_QUIT’ randomly to the child thread. iii.The child thread processes the message posted by the main thread and quits when it receives the ‘WM_QUIT’ messge. iv.The main thread checks the termination of the child thread and quits when the child thread complete its execution. v.The main thread continues sending the random messages to the child thread till the ‘WM_QUIT’ message is sent to child thread. vi.The messaging mechanism between the main thread and child thread is synchronous.5.Test the program application for creating an anonymous pipe with 512bytes of size and pass the ‘Read Handle’ of the pipe to a second processusing memory mapped object. The first process writes a message ‘ Hi fromPipe Server’. The 2nd process reads the data written by the pipe server to thepipe and displays it on the console. Use event object for indicating theavailability of data on the pipe and mutex objects for synchronizing theaccess in the pipe.6.Create a POSIX based message queue for communicating between twotasks as per the requirements given below:- i.Use a named message queue with name ‘MyQueue’. ii.Create two tasks(Task1 & Task2) with stack size 4000 & priorities 99 & 100 respectively. iii.Task 1 creates the specified message queue as Read Write and reads the message present, if any, from the message queue and prints it on the console. iv.Task2 open the message queue and posts the message ‘Hi from Task2’.Handle all possible error scenarios appropriately.--------------------------------------------------------------------------- VLSI Design Verification Subject Code : 12EC130 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Note: Today, the complexity of the VLSI integrated circuits that are beingdesigned is so large that pre-silicon verification presents a major challenge tothe design team. The fact that IP from multiple sources are integrated todayto create a system-on-chip design further complicates the matter. Simulation 9
  10. 10. based verification techniques that were developed in the past are consideredinadequate to-day, since they require too many test cases and require toomuch development time and run-time. Raising the level of abstraction todesign can help bring down the simulation cost. Formal specification andverification techniques are another way to address the challenge of designverification.Importance of Design Verification: What is verification? What is atestbench? The importance of verification, Reconvergence model, Formalverification, Equivalence checking, Model checking, Functional verification.Functional verification approaches: Black box verification, white boxverification, grey box verification. Testing versus verification: scan basedtesting, design for verification. Verification reuse. The cost of verification.[Ref1- Chapter1] Verification Tools: Linting tools: Limitations of linting tools, linting verilogsource code, linting VHDL source code, linting OpenVera & e source code,code reviews. Simulators: Stimulus and response, Event based simulation,cycle based simulation, Co-simulators, verification intellectual property:hardware modelers, waveform viewers, Code Coverage: statement coverage,path coverage, expression coverage, FSM coverage, what does 100%coverage mean? Functional coverage: Item Coverage, cross coverage,Transition coverage , what does 100% functional mean? Verificationallanguages: Assertions: simulation based assertions, formal assertions proving.Metrics: Code related metrics, Quality related metrics, interpretingmetrics.[Ref1-Chapter2] The verification plan: The role of verification plan: specifying theverification plan, defining the first success. Levels of verification: unit levelverification, reusable components verification, ASIC and FPGA verification,system level verification, board level verification, verifying stratergies,verifying responses, From specification to features: component level feature,system level features, Error types to look for?, prioritise, design forverification. Directed testbench approaches group into testcases, fromtestcases to testbenches, measuring progress.Coverage driven random basedapproach: Measuring progress,From features to functional coverage,fromfeatures to testbench, From features to generators, directed testcases. [Ref1-Chapter3] 10
  11. 11. Static Timing Verification. Concept of static timing analysis. Cross talk andnoise. Limitations of STA. slew of a waveform,Skew between thesignals,Timing arcs and unateness, Min and Max timing paths,clockdomains,operating conditions,critical path analysis,false paths,Timingmodels. [Ref2 Chapter 1, 2,3,8] Physical Design Verification. Layout rule checks and electrical rule checks.Parasitic extraction. Antenna[Ref4 Chapter 8] Crosstalk and Noise: Cross talk glitch analysis, crosstalk delayanalysis,timing verification [Ref4 Chapter 8] IP-Reuse in modern-day SoC. SoC Integration and the problem ofverification of IP-based designs. Verification IP and their importance. (Ref.5)Formal Verification: SAT BDDs, Symbolic Model Checking with BDDs,Model Checking using SAT, Equivalence Checking. [Ref3 Chapter 1, 2]REFERENCE BOOKS: 1. Writing testbenches: functional verification of HDL models. Janick nd Bergeron, 2 edition ,Kluwer Academic Publishers,2003 2. Static Timing Analysis for Nanometer Designs: A practical approach Jayaram Bhasker,Rakesh Chadha, Springer publications 3. S.Minato “ Binary decision diagram and applications for VLSI CAD”, Kulwer Academic pub November 1996 4. “System on a Chip Verification” Prakash Rashinkar, Peter Paterson,Leena Singh, Kulwer Publications. 5. http://www.cse.psu.edu/~vijay/verify/instuctors.html 11
  12. 12. ELECTIVE – I DIGITAL SYSTEM DESIGN USING VERILOG Subject Code : 12EC121 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Introduction and Methodology:Digital Systems and Embedded Systems, Binary representation and CircuitElements, Real-World Circuits, Models, Design Methodology.Combinational Basics:Boolean Functions and Boolean Algebra, Binary Coding, CombinationalComponents and Circuits, Verification of Combinational Circuits.Number Basics:Unsigned and Signed Integers, Fixed and Floating-point Numbers.Sequential Basics: Storage elements, Counters, Sequential Datapaths andControl, Clocked Synchronous Timing Methodology.Memories: Concepts, Memory Types, Error Detection and Correction.Implementation Fabrics: ICs, PLDs, Packaging and Circuit Boards,Interconnection and Signal Integrity.Processor Basics: Embedded Computer Organization, Instruction and Data,Interfacing with memory.I/O interfacing: I/O devices, I/O controllers, Parallel Buses, SerialTransmission, I/O software.Accelerators: Concepts, case study, Verification of accelerators.Design Methodology: Design flow, Design optimization, Design for test,Reference Books: 1.“Digital Design: An Embedded Ssytems Approach Using VERILOG”, Peter J. Ashenden, Elesvier, 2010. 12
  13. 13. NANOELECTRONICS Subject Code : 12EC054 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Introduction: Overview of nanoscience and engineering,Developmentmilestones in microfabrication and electronic industry,Moores law andcontinued miniaturization,Classification of Nano structures,Electronicproperties of atoms and solids: Isolated atom, Bonding between atoms,Giantmolecular solids,Free electron models and energy bands,crystalline solids,Periodicity of crystal lattices, Electronic conduction,effects of nanometerlength scale,Fabrication methods: Top down processes,Bottom up processesmethods for templating the growth of nanomaterials, ordering ofnanosystems.Characterization: Classification, Microscopic techniques, Field ionmicroscopy, scanning probe techniques, diffraction techniques: bulk ,surface,spectroscopy techniques: photon, radiofrequency, electron, surface analysisand dept profiling: electron, mass, Ion beam, Reflectrometry, Techniques forproperty measurement: mechanical, electron, magnetic, thermal properties.Inorganic semiconductor nanostructures: overview of semiconductorphysics,Quantum confinement in semiconductor nanostructures: quantumwells ,quantum wires, quantum dots, super-lattices, band offsets,electronicdensity of states.Fabrication techniques: requirements of ideal semiconductor,epitaxialgrowth of quantum wells, lithography and etching,cleaved edgeovergrowth,growth of vicinal substrates,strain induced dots andwires,electrostatically induced dots and wires,Quantum well widthfluctuations,thermally annealed quantum wells,semiconductornanocrystals,collidal quantum dots,self-assembly techniques.Physical processes: modulation doping,quantum hall effect,resonanttunneling,charging effects,ballistic carrier transport,Inter band absorption,intraband absorption,Light emission processes,phonon bottleneck, quantum 13
  14. 14. confined stark effect,nonlinear effects,coherence and dephasing,characterization of semiconductor nanostructures:optical electrical andstructural.Methods of measuring properties:structure:atomic,crystallography,microscopy,spectroscopy. Properties of nanoparticles:metal nano clusters, semiconducting nanoparticles, rare gas and molecularclusters, methods of synthesis(RF, chemical, thermolysis,pulsed lasermethods) Carbon nanostructures and its applications(field emission andshielding,computers,fuel cells,sensors,catalysis).Self assemblingnanostructured molecular materials and devices: building blocks,principlesof self assembly, methods to prepare and pattern nanoparticles,templatednanostructures,liquid crystal mesophases.Nanomagnetic materials anddevices:magnetism,materials,magneto resistance,nanomagnetism intechnology,challenges facing nano magnetism. Applications: Injection lasers,quantum cascade lasers,singe photonsources,biological tagging,optical memories,coulomb blocadedevices,photonic structures,QWIP’s,NEMS,MEMS.References:1.Ed Robert Kelsall,Ian Hamley,Mark Geoghegan, “ Nanoscale science andtechnology” ,John wiley and sons,2007.2.Charles P Poole,Jr,Frank J owens “Introduction to Nanotechnology”,John wiley,copyright 2006,Reprint 2011.3.Ed William A Goddard III,Donald W Brenner,Sergey EdwardLyshevski,Gerald J Lafrate, “ Hand Book of Nanoscience Engineering andTechnology” ,CRC press,2003. ASIC DESIGN Subject Cod : 12EC012 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Note: All Designs Will Be Based On VHDL 14
  15. 15. Introduction: Full Custom with ASIC, Semi custom ASICS, Standard Cellbased ASIC, Gate array based ASIC, Channeled gate array, Channel less gatearray, structured get array, Programmable logic device, FPGA design flow,ASIC cell librariesData Logic Cells: Data Path Elements, Adders, Multiplier, ArithmeticOperator, I/O cell, Cell CompilersASIC Library Design: Logical effort: practicing delay, logical area andlogical efficiency logical paths, multi stage cells, optimum delay, optimumno. of stages, library cell design.Low-Level Design Entry: Schematic Entry: Hierarchical design. The celllibrary, Names, Schematic, Icons & Symbols, Nets, schematic entry forASIC’S, connections, vectored instances and buses, Edit in place attributes,Netlist, screener, Back annotationProgrammable ASIC: programmable ASIC logic cell, ASIC I/O cellA Brief Introduction to Low Level Design Language: an introduction toEDIF, PLA Tools, an introduction to CFI designs representation. Half gateASIC. Introduction to Synthesis and Simulation;ASIC Construction Floor Planning and Placement And Routing:Physical Design, CAD Tools, System Partitioning, Estimating ASIC size,partitioning methods. Floor planning tools, I/O and power planning, clockplanning, placement algorithms, iterative placement improvement, Timedriven placement methods. Physical Design flow global Routing, LocalRouting, Detail Routing, Special Routing, Circuit Extraction and DRC.EFERENCE BOOKS: 1.M.J.S .Smith, - “Application - Specific Integrated Circuits” – Pearson Education, 2003. 2. Jose E.France, Yannis Tsividis, “Design of Analog-Digital VLSI Circuits for Telecommunication and signal processing”, Prentice Hall, 1994. 3.Malcolm R.Haskard; Lan. C. May, “Analog VLSI Design - NMOS and CMOS”, Prentice Hall, 1998. 4.Mohammed Ismail and Terri Fiez, “Analog VLSI Signal and Information Processing”, McGraw Hill, 1994. 15
  16. 16. II – SEMESTER DESIGN OF ANALOG & MIXED MODE VLSI CIRCUITS Subject Code : 12EC025 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100 MOSFET Modelling for Basic Analog Design: Derivation of MOS I/VCharacteristics(ID ,RON,gm), second order effects, MOS device Models.[Ref 1. Chapter 2] Single stage Amplifier: CS stage with resistive load, diode connected load,current source load, triode load, CS stage with source degeneration, Sourcefollower, Common-gate stage, Cascode stage, Folded Cascode, Choice ofdevice models. [Ref 1. Chapter 3] Frequency Response of CS Stage: General considerations: Miller effect,Association of poles with nodes, Frequency response of Common SourceStage. [Ref 1. Chapter 6]Differential Amplifiers & Current Mirrors: Basic differential Pair,Common mode response, Differential pair with MOS loads, Gilbert cell.Basic current mirrors, Cascode Current mirrors, Active currentmirrors. [Ref 1. Chapter 4, 5] Operational Amplifiers: One Stage OP-Amp. Two Stage OP-Amp, Gainboosting, Common Mode Feedback, Slew Rate, Power Supply Rejection,Noise in Op Amps. [Ref 1. Chapter 9] Oscillators & Phase Locked Loop: Ring Oscillators, LC Oscillators, VCO, Mathematical Model of VCO. Simple PLL, Charge pump PLL, Non-ideal effects in PLL, Delay locked loops and applications. [Ref 1. Chapter 14, 15] 16
  17. 17. Bandgap Reference & Switched Capacitor Circuits: GeneralConsiderations, Supply Independent biasing, Temperature independentbiasing, PTAT Current Generation, Constant Gm biasing. SamplingSwitches, Switched Capacitor Amplifiers. [Ref 1. Chapter 11, 12]Data Converter Architectures: DAC & ADC Specifications, (QualitativeAnalysis of )Resistor String DAC, R-2R Ladder Networks, Current SteeringDAC, Charge Scaling DAC, Cyclic DAC, Pipeline DAC, Flash ADC,Pipeline ADC, Integrating ADC, Successive Approximation ADC. [Ref 2.Chapter 28,29]REFERENCE BOOK:1. Behzad Razavi,“Design of Analog CMOS Integrated Circuits”,TMH, 2007.2. R.Jacob Baker,“CMOS Circuit Design, Layout, and Simulation”, VolII, Second Edition, Wiley.3. Phillip E. Allen, Douglas R. Holberg,“CMOS Analog Circuit Design”,Second Edition, Oxford University Press.LABORATORY EXPERIMENTS:ALL EXPERIMENTS MUST BE IMPLEMENTED USING VLSI TOOLSLIKE CADANCE/SYNOPSIS/MENTAGRAPHICS.1. Design the MOS transistor circuits for DC & AC small signal parameters, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS.2. Design a TWO stage op-amp with given specification* using givendifferential amplifier Common source and Common Drain amplifier inlibrary** and completing the design flow mentioned below: a. Draw the schematic and verify the following 17
  18. 18. i) DC Analysis ii). AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for frequency response, slew rate, offset effects and Noise.3. Design a simple sample and hold circuit and measure the switchingtimes.4. Design a PLL and measure all the parameters.5. Design a simple ADC/DAC and measure the data conversion time. Assume the 95 nanometer technology.6. Design 3-8 decoder using MOS technology.ANY EXPERIMETNS CAN BE ADDED TO SUPPLEMENT THETHEORY. ABOVE IS THE ONLY GUIDE LINES. --------------------------------------------- REAL TIME OPERATING SYSTEMS Subject Code : 12EC126 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Introduction to Real-Time Embedded Systems: Brief history of RealTime Systems, A brief history of Embedded Systems.System Resources: Resource Analysis, Real-Time Service Utility,Scheduling Classes, The Cyclic Esecutive, Scheduler Concepts, PreemptiveFixed Priority Scheduling Policies, Real-Time OS, Thread Safe ReentrantFunctions.Processing: Preemptive Fixed-Priority Policy, Feasibility, Rate Montonicleast upper bound, Necessary and Sufficient feasibility, Deadline –Monotonic Policy, Dynamic priority policies.I/O Resources: Worst-case Execution time, Intermediate I/O, Executionefficiency, I/O Architecture.Memory: Physical hierarchy, Capacity and allocation, Shared Memory,ECC Memory, Flash file systems. 18
  19. 19. Multi-resource Services:Blocking, Deadlock and livestock, Critical sections to protect sharedresources, priority inversion.Soft Real-Time Services:Missed Deadlines, QoS, Alternatives to rate monotonic policy, Mixed hardand soft real-time services.Embedded System Components:Firmware components, RTOS system software mechanisms, Softwareapplication components.Debugging Components:Execptions assert, Checking return codes, Single-step debugging, kernelscheduler traces, Test access ports, Trace ports, Power-On self test anddiagnostics, External test equipment, Application-level debugging.Performance Tuning:Basic concepts of drill-down tuning, hardware – supported profiling andtracing, Building performance monitoring into software, Path length,Efficiency, and Call frequency, Fundamental optimizations.High availability and Reliability Design:Reliability and Availability, Similarities and differences, Reliability, Reliablesoftware, Available software, Design trade offs, Hierarchical applications forFail-safe design.Design of RTOS – PIC microcontroller. (Chap 13 of book Myke Predko)Reference Books: 1.“Real-Time Embedded Systems and Components” , Sam Siewert, Cengage Learning India Edition, 2007. 2.“ Programming and Customizing the PIC microcontroller” , Myke Predko, 3rd Ed, TMH, 2008. 3.“Programming for Embedded Systems”, Dreamtech Software Team, Jhon Wiley, India Pvt. Ltd., 2008.Real Time Operating Systems:Laboratory Experiments - 19
  20. 20. (Reference Book 3 can be used to give Lab. Assignments)USE LINUX/SOLARIS/QNX OS ONLY.1. Implement simple IPC protocol.2. Implement Semaphore and Mutex for any given applications.3. Communicate between 2 PCs using Socket programming or message passing techniques (ie., MPI). 4.Create ‘n’ number of child threads. Each thread prints the message “ I’m in thread number …” and sleeps for 50 ms and then quits. The main thread waits for complete execution of all the child threads and then quits. Compile and execute in Linux.5. Implement the multithread application satisfying the following : i. Four child threads are crated with normal priority. ii. Thread 1& 2 receives and prints its priority and sleeps for 50ms and then quits. iii. Thread 3&4 prints the priority of the thread 1 &2 and rises its priority to above normal and retrieves the new priority of thread 1, prints it and then quits. iv. The main thread waits for the child thread to complete its job and quits.6. Implement the usage of send and receive primitives with 512 bytes fordata sharing between parent and child processes using handle inheritancemechanism.7. Test the program below using multithread application- 1.The main thread creates a child thread with default stack size and name ‘Child_Thread’. 2.The main thread sends user defined messages and the message ‘WM_QUIT’ randomly to the child thread. 3.The child thread processes the message posted by the main thread and quits when it receives the ‘WM_QUIT’ messge. 4.The main thread checks the termination of the child thread and quits when the child thread complete its execution. 5.The main thread continues sending the random messages to the child thread till the ‘WM_QUIT’ message is sent to child thread. 6.The messaging mechanism between the main thread and child thread is synchronous.8. Test the program application for creating an anonymous pipe with 512bytes of size and pass the ‘Read Handle’ of the pipe to a second process usingmemory mapped object. The first process writes a message ‘ Hi from Pipe 20
  21. 21. Server’. The 2nd process reads the data written by the pipe server to the pipeand displays it on the console. Use event object for indicating the availabilityof data on the pipe and mutex objects for synchronizing the access in thepipe. For synchronization semaphore/mutex can be used.9. Create a POSIX based message queue for communicating betweenseveral tasks as per the requirements given below:- i. Use a named message queue with name ‘MyQueue’. ii. Create N tasks with stack size 4000 & priorities (n-1) & n respectively. N can be any number but more than 4. iii. Tasks creates the specified message queue as Read Write and reads the message present, if any, from the message queue and prints it on the console. iv. Tasks open the message queue and posts the message ‘Hi from Task(n-1)’. v.Handle all possible error scenarios appropriately. MINI PROJECTS: (optional) 1. Implement protocol converter (refer book 3 given in the RTOS theory) 2. Implement System Calls for the RTOS using RTLinux. 3. Implement an IP phone. 4. Implement Device Driver.ANY EXPERIMETNS CAN BE ADDED TO SUPPLEMENT THETHEORY. ABOVE IS THE ONLY GUIDE LINES. ------------------------------------------------------- ADVANCED MICROCONTROLLERS Subject Code : 12EC116 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Note: Microcontrollers have become prevalent in a number of applicationssuch as instrumentation, industrial electronics, automotive electronics,robotics, etc. Advances in VLSI technology permit the integration of not onlythe processor but also the analog electronics, memory and peripheralsnecessary for system implementation; this allows low-cost systemimplementation. Some microcontrollers used in industrial electronics also 21
  22. 22. provide some digital signal processing capability to further reduce thesystem cost.Power dissipation is often a consideration in many systems and modernmicrocontrollers address it through the support of several low-power modesof operation. The aim of the course is to introduce advanced microcontrollers(16-bit and 32-bit).Motivation for advanced microcontrollers – Low Power embeddedsystems, On-chip peripherals, low-power RF capabilities. Examples ofapplications.MSP430 – 16-bit Microcontroller family. CPU architecture, Instruction set,Interrupt mechanism, Clock system, Memory subsystem, bus –architecture.The assembly language and ‘C’ programming for MSP-430microcontrollers. On-chip peripherals. WDT, Comparator, Op-Amp, Timer,Basic Timer, Real Time Clock (RTC), ADC, DAC, Digital I/O. Using thelow-power features of MSP430. Clock system, low-power modes, Clockrequest feature, Low-power programming and interrupts.ARM -32 bit Microcontroller family. Architecture of ARM Cortex M3 –General Purpose Registers, Stack Pointer, Link Register, Program Counter,Special Register,. Nested Vector Interrupt Controller. Interrupt behavior ofARM Cortex M3. Exceptions Programming. Advanced ProgrammingFeatures. Memory Protection. Debug Architecture.Applications – Wireless Sensor Networking with MSP430 and Low-PowerRF circuits; Pulse Width Modulation(PWM) in Power Supplies.References Books: 1.Joseph Yiu “ The Definitive Guide to the ARM Cortex-M3, , Newnes, (Elsevier), 2008. 2.John Davies, “ MSP430 Microcontorller Basics”, Newnes (Elsevier Science), 2008. 3.MSP430 Teaching CD-ROM, Texas Instruments, 2008. 4.Sample Programs for MSP430 downloadable from msp430.com 5.David Patterson and John L. Henessay, “Computer Organization and Design”, (ARM Edition), Morgan Kauffman. 22
  23. 23. LOW POWER VLSI DESIGN Subject Code : 12EC047 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Introduction : Need for low power VLSI chips, Sources of power dissipationon Digital Integrated circuits. Emerging Low power approaches, Physics ofpower dissipation in CMOS devices.Device & Technology Impact on Low Power: Dynamic dissipation inCMOS, Transistor sizing & gate oxide thickness, Impact of technologyScaling, Technology & Device innovationPower estimation, Simulation Power analysis: SPICE circuit simulators,gate level logic simulation, capacitive power estimation, static state power,gate level capacitance estimation, architecture level analysis, data correlationanalysis in DSP systems, Monte Carlo simulation.Probabilistic power analysis: Random logic signals, probability &frequency, probabilistic power analysis techniques, signal entropy.Low Power Design Circuit level: Power consumption in circuits. Flip Flops& Latches design, high capacitance nodes, low power digital cells libraryLogic level: Gate reorganization, signal gating, logic encoding, state machineencoding, pre-computation logicLow power Architecture & Systems: Power & performance management,switching activity reduction, parallel architecture with voltage reduction,flow graph transformation, low power arithmetic components, low powermemory design.Low power Clock Distribution: Power dissipation in clock distribution,single driver Vs distributed buffers, Zero skew Vs tolerable skew, chip &package co design of clock networkAlgorithm & Architectural Level Methodologies: Introduction, designflow, Algorithmic level analysis & optimization, Architectural levelestimation & synthesis. 23
  24. 24. REFERENCE BOOKS: 1.Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley, 2000 2.Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002 3.Rabaey, Pedram, “Low Power Design Methodologies” Kluwer Academic, 1997 ELECTIVE –II DESIGN OF VLSI SYSTEMS Subject Code : 12EC027 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100VLSI System Design Methodology: Structure Design, Strategy, Hierarchy,Regularity, Modularity, and Locality. System on Chip Design options:Programmable logic and structures, Programmable interconnect,programmable gate arrays, Sea of gate and gate array design, standard celldesign, full custom mask design.Chip Design Methods: Behavioral synthesis, RTL synthesis, Logicoptimization and structural tools layout synthesis, layout synthesis, EDATools for SystemDesign Capture Tools: HDL Design, Schematic Design, Layout Design,Floor planning and Chip Composition. Design Verification Tools: SimulationTiming Verifiers, Net List Comparison Layout Extraction, Design RuleVerification.Data Path Sub System Design: Introduction, Addition, Subtraction,Comparators, Counters, Boolean logical operations, coding, shifters,Multiplication, Parallel Prefix computationsArray Subsystem Design: SRAM, Special purpose RAMs, DRAM, Readonly memory, Content Addressable memory, Programmable logic arrays.Control Unit Design: Finite State Machine (FSM) Design, Control LogicImplementation: PLA control implementation, ROM control implementation. 24
  25. 25. Special Purpose Subsystems: Packaging, power distribution, I/O, Clock,Transconductance amplifier, follower integrated circuits, etcDesign Economics: Nonrecurring and recurring engineering Costs, FixedCosts, Schedule, Person power, exampleVLSI System Testing & Verification: Introduction, A walk through theTest Process, Reliability, Logic Verification Principles, Silicon DebugPrinciples, Manufacturing Test Principles, Design for Testability, BoundaryScanVLSI Applications: Case Study: RISC microcontroller, ATM Switch,etc.REFERENCE BOOKS: 1. Neil H.E. Weste, Davir Harris, “CMOS VLSI Design: A Circuits and System Perspectives” Addison Wesley - Pearson Education, 3rd Edition, 2004. 2. Wayne, Wolf, “Modern VLSI Design: System on Silicon” Prentice Hall PTR/Pearson Education, Second Edition, 1998 3. Douglas A Pucknell & Kamran Eshragian , “Basic VLSI Design” PHI 3rd Edition (original Edition – 1994). VLSI DESIGN AUTOMATION Subject Code : 12EC010 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Logic Synthesis & Verification: Introduction to combinational logicsynthesis, Binary Decision Diagram, Hardware models for High-levelsynthesis.VLSI Automation Algorithms:Partitioning: problem formulation, classification of partitioning algorithms,Group migration algorithms, simulated annealing & evolution, otherpartitioning algorithms 25
  26. 26. Placement, Floor Planning & Pin Assignment: problem formulation,simulation base placement algorithms, other placement algorithms, constraintbased floor planning, floor planning algorithms for mixed block & celldesign. General & channel pin assignmentGlobal Routing: Problem formulation, classification of global routingalgorithms, Maze routing algorithm, line probe algorithm, Steiner Tree basedalgorithms, ILP based approachesDetailed Routing: problem formulation, classification of routing algorithms,single layer routing algorithms, two layer channel routing algorithms, threelayer channel routing algorithms, and switchbox routing algorithmsOver The Cell Routing & Via Minimization: two layers over the cellrouters, constrained & unconstrained via minimizationCompaction: problem formulation, one-dimensional compaction, twodimension based compaction, hierarchical compactionREFERENCE BOOKS: 1. Naveed Shervani, “Algorithms for VLSI physical design Automation”, Kluwer Academic Publisher, Second edition. 2.Christophn Meinel & Thorsten Theobold, “Algorithm and Data Structures for VLSI Design”, KAP, 2002. 3.Rolf Drechsheler : “Evolutionary Algorithm for VLSI”, Second edition 4.Trimburger, “Introduction to CAD for VLSI”, Kluwer Academic publisher, 2002 MODERN DSP Subject Code : 12EC123 IA Marks : 50 No. of Lecture Hours/Week : 04 Exam Marks : 03 Total No. of Lecture Hours : 52 Exam Hours : 100Goal of the course – Advances in Digital Signal Processing involve variablesampling rates and thus the multirate signal processing and hence their 26
  27. 27. applications in communication systems and signal processing. It is intendedto introduce a basic course in multirate signal processing especially meantfor students of branches eligible for M Tech courses in EC relateddisciplines.Introduction and Discrete Fourier Transforms: Signals, Systems andProcessing, Classification of Signals, The Concept of Frequency inContinuous-Time and Discrete-Time Signals, Analog-to-Digital and Digital-to-Analog Conversion, Frequency-Domain Sampling: The Discrete FourierTransform, Properties of the DFT, Linear Filtering Methods Based on theDFT (Ref.1 Chap. 1 & 7)Design of Digital Filters: General Considerations, Design of FIR Filters,Design of IIR Filters from Analog Filters, Frequency Transformations. (Ref.1Chap.10)Multirate Digital Signal Processing: Introduction, Decimation by a factor‘D’, Interpolation by a factor ‘I’, Sampling rate Conversion by a factor ‘I/D’,implementation of Sampling rate conversion, Multistage implementation ofSampling rate conversion, Sampling rate conversion of Band Pass Signals,Sampling rate conversion by an arbitrary factor, Applications of MultirateSignal Processing, Digital Filter banks, Two Channel Quadrature MirrorFilter banks, M-Channel QMF bank. (Ref.1 Chap.11) Adaptive Filters: Applications of Adaptive Filters, Adaptive Direct FormFIR Filters- The LMS Algorithm, Adaptive Direct Form Filters-RLSAlgorithm. (Ref.1 Chap.13)References:1. Proakis and Manolakis, “Digital Signal Processing”, Prentice Hall 1996.(fourth edition).2. Roberto Cristi, “Modern Digital Signal Processing”, CengagePublishers, India, (erstwhile Thompson Publications), 2003. 3. S.K. Mitra, “Digital Signal Processing: A Computer Based Approach”,III Ed, Tata McGraw Hill, India, 2007.4. E.C. Ifeachor and B W Jarvis, “Digital Signal Processing, apractitioners approach,” II Edition, Pearson Education, India, 2002 Reprint. 27
  28. 28. III – SEMESTER CMOS RF CIRCUIT DESIGN Subject Code : 12EC020 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Introduction to RF Design and Wireless Technology: Design andApplications, Complexity and Choice of Technology. Basic concepts in RFdesign: Nonlinearly and Time Variance, Intersymbol interference, randomprocesses and noise. Sensitivity and dynamic range, conversion of gains anddistortion.RF Modulation: Analog and digital modulation of RF circuits, Comparisonof various techniques for power efficiency, Coherent and non-coherentdetection, Mobile RF communication and basics of Multiple Accesstechniques. Receiver and Transmitter architectures, Direct conversion andtwo-step transmitters. RF Testing: RF testing for heterodyne, Homodyne,Image reject, Direct IF and sub sampled receivers.BJT and MOSFET Behavior at RF Frequencies: BJT and MOSFETbehavior at RF frequencies, modeling of the transistors and SPICE model,Noise performance and limitations of devices, integrated parasitic elements athigh frequencies and their monolithic implementation.Circuits Design: Overview of RF Filter design, Active RF components &modeling, Matching and Biasing Networks. Basic blocks in RF systems andtheir VLSI implementation, Low noise Amplifier design in varioustechnologies, Design of Mixers at GHz frequency range, Various mixers-working and implementation. Oscillators- Basic topologies VCO anddefinition of phase noise, Noise power and trade off. Resonator VCOdesigns, Quadrature and single sideband generators. Radio frequencySynthesizers- PLLS, Various RF synthesizer architectures and frequencydividers, Power Amplifier design, Liberalization techniques, Design issues inintegrated RF filters. 28
  29. 29. REFERENCE BOOKS: 1.B. Razavi, “RF Microelectronics” PHI 1998 2.R. Jacob Baker, H.W. Li, D.E. Boyce “CMOS Circuit Design, layout and Simulation”, PHI 1998. 3.Thomas H. Lee “Design of CMOS RF Integrated Circuits” Cambridge University press 1998. 4.Y.P. Tsividis, “Mixed Analog and Digital Devices and Technology”, TMH 1996 ELECTIVE - III SYNTHESIS AND OPTIMIZATION OF DIGITAL CIRCUITS Subject Code : 12EC077 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Introduction: Microelectronics, semiconductor technologies and circuittaxonomy, Microelectronic design styles, computer aided synthesis andoptimization.Graphs: Notation, undirected graphs, directed graphs, combinatorialoptimization, Algorithms, tractable and intractable problems, algorithms forlinear and integer programs, graph optimization problems and algorithms,Boolean algebra and Applications.Hardware Modeling: Hardware Modeling Languages, distinctive features,structural hardware language, Behavioral hardware language, HDLs used insynthesis, abstract models, structures logic networks, state diagrams, dataflow and sequencing graphs, compilation and optimization techniques.Two Level Combinational Logic Optimization: Logic optimization,principles, operation on two level logic covers, algorithms for logicminimization, symbolic minimization and encoding property, minimizationof Boolean relations. 29
  30. 30. Multiple Level Combinational Optimizations: Models and transformationsfor combinational networks, algebraic model, Synthesis of testable network,algorithm for delay evaluation and optimization, rule based system for logicoptimization.Sequential Circuit Optimization: Sequential circuit optimization using statebased models, sequential circuit optimization using network models.Schedule Algorithms: A model for scheduling problems, Scheduling withresource and without resource constraints, Scheduling algorithms forextended sequencing models, Scheduling Pipe lined circuits.Cell Library Binding: Problem formulation and analysis, algorithms forlibrary binding, specific problems and algorithms for library binding (lookuptable F.P.G.As and Antifuse based F.P.G.As), rule based library binding.Testing: Simulation, Types of simulators, basic components of a simulator,fault simulation Techniques, Automatic test pattern generation methods(ATPG), design for Testability (DFT) Techniques.REFERENCE BOOKS: 1.Giovanni De Micheli, “Synthesis and Optimization of Digital Circuits”, Tata McGraw-Hill, 2003. 2.Srinivas Devadas, Abhijit Ghosh, and Kurt Keutzer, “Logic Synthesis”, McGraw-Hill, USA, 1994. 3.Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: A System Perspective,” 2nd edition, Pearson Education (Asia) Pte. Ltd., 2000. 4.Kevin Skahill, “VHDL for Programmable Logic,” Pearson Education (Asia) Pvt. Ltd., 2000. IMAGE AND VIDEO PROCESSING Subject Code : 12EC043 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Introduction: 2D systems, Mathematical preliminaries – Fourier Transform,Z Transform, Optical & Modulation transfer function, Matrix theory, 30
  31. 31. Random signals, Discrete Random fields, Spectral density function.(Ref.1,Chap.2)Image Perception: Light, Luminance, Brightness, Contrast, MTF of thevisual system, Visibility function, Monochrome vision models, Fidelitycriteria, Color representation, Chromaticity diagram, Color coordinatesystems, Color difference measures, Color vision model, Temporal propertiesof vision. (Ref.1, Chap.3)Image Sampling and Quantization: Introduction, 2D sampling theory,Limitations in sampling & reconstruction, Quantization, Optimal quantizer,Compander, Visual quantization. (Ref.1, Chap.4)Image Transforms: Introduction, 2D orthogonal & unitary transforms,Properties of unitary transforms, DFT, DCT, DST, Hadamard, Haar, Slant,KLT, SVD transform. (Ref.1, Chap.5)Image Representation by Stochastic Models: Introduction, one-dimensional Causal models, AR models, Non-causal representations, linearprediction in two dimensions. (Ref.1, Chap.6)Image Enhancement: Point operations, Histogram modeling, spatialoperations, Transform operations, Multi-spectral image enhancement, falsecolor and Pseudo-color, Color Image enhancement. (Ref.1, Chap.7)Image Filtering & Restoration: Image observation models, Inverse &Wiener filtering, Fourier Domain filters, Smoothing splines and interpolation,Least squares filters, generalized inverse, SVD and Iterative methods,Maximum entropy restoration, Bayesian methods, Coordinate transformation& geometric correction, Blind de-convolution. (Ref.1, Chap.8)Image Analysis & Computer Vision: Spatial feature extraction, Transformfeatures, Edge detection, Boundary Extraction, Boundary representation,Region representation, Moment representation, Structure, Shape features,Texture, Scene matching & detection, Image segmentation, ClassificationTechniques. (Ref.1, Chap.9)Image Reconstruction from Projections: Introduction, Radon Transform,Back projection operator, Projection theorem, Inverse Radon transform,Fourier reconstruction, Fan beam reconstruction, 3D tomography. (Ref.1,Chap.10)Image Data Compression: Introduction, Pixel coding, Predictivetechniques, Transform coding, Inter-frame coding, coding of two toneimages, Image compression standards. (Ref.1, Chap.11)Video Processing: Fundamental Concepts in Video – Types of video signals,Analog video, Digital video, Color models in video, Video CompressionTechniques – Motion compensation, Search for motion vectors, H.261, 31
  32. 32. H.263, MPEG I, MPEG 2, MPEG 4, MPEG 7 and beyond, Content basedvideo indexing. (Ref.4)Reference Books:1. K. Jain, “Fundamentals of Digital Image Processing," PearsonEducation (Asia) Pte. Ltd./Prentice Hall of India, 2004.2. Z. Li and M.S. Drew, “Fundamentals of Multimedia,” PearsonEducation (Asia) Pte. Ltd., 2004.3.R. C. Gonzalez and R. E. Woods, “Digital Image Processing,” 2nd edition,Pearson Education (Asia) Pte. Ltd/Prentice Hall of India, 2004.4. M. Tekalp, “Digital Video Processing,” Prentice Hall, USA, 1995. AUTOMOTIVE ELECTRONICS Subject Code :12EC117 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Automotive Fundamentals Overview – Four Stroke Cycle, EngineControl, Ignition System, Spark plug, Spark pulse generation, IgnitionTiming, Drive Train, Transmission, Brakes, Steering System, Battery,Starting System. sAir/Fuel Systems – Fuel Handling, Air Intake System, Air/ FuelManagementSensors – Oxygen (O2/EGO) Sensors, Throttle Position Sensor (TPS),Engine Crankshaft Angular Position (CKP) Sensor, Magnetic ReluctancePosition Sensor, Engine Speed Sensor, Ignition Timing Sensor, Hall effectPosition Sensor, Shielded Field Sensor, Optical Crankshaft Position Sensor,Manifold Absolute Pressure (MAP) Sensor - Strain gauge and Capacitorcapsule, Engine Coolant Temperature (ECT) Sensor, Intake Air Temperature(IAT) Sensor, Knock Sensor, Airflow rate sensor, Throttle angle sensorActuators – Fuel Metering Actuator, Fuel Injector, Ignition ActuatorExhaust After-Treatment Systems – AIR, Catalytic Converter, ExhaustGas Recirculation (EGR), Evaporative Emission Systems. 32
  33. 33. Electronic Engine Control – Engine parameters, variables, EnginePerformance terms, Electronic Fuel Control System, Electronic Ignitioncontrol, Idle sped control, EGR ControlCommunication – Serial Data, Communication Systems, Protection, Bodyand Chassis Electrical Systems, Remote Keyless Entry, GPS.Vehicle Motion Control – Cruise Control, Chassis, Power Brakes, AntilockBrake System (ABS), Electronic Steering Control, Power Steering, TractionControl, Electronically controlled suspensionAutomotive Instrumentation – Sampling, Measurement & SignalConversion of various parameters.Integrated Body – Climate Control Systems, Electronic HVAC Systems,Safety Systems – SIR, Interior Safety, Lighting, Entertainment SystemsAutomotive Diagnostics – Timing Light, Engine Analyzer, On-boarddiagnostics, Off-board diagnostics, Expert Systems.Future Automotive Electronic Systems – Alternative Fuel Engines,Collision Avoidance Radar warning Systems, Low tire pressure warningsystem, Radio navigation, Advance Driver Information SystemReference Books: - 1.William B. Ribbens: Understanding Automotive Electronics, 6th Edition, SAMS/Elsevier Publishing 2.Robert Bosch GmbH: Automotive Electrics Automotive Electronics Systems and Components, 5th edition, John Wiley& Sons Ltd., 2007. ELECTIVE-IV RF AND MICROWAVE CIRCUIT DESIGN Subject Code : 12EC071 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Wave Propagation in N/W:Introduction, reasons for using RF/Micro waves, applications, RF waves, RFand Microwave circuit design, introduction to component basics, analysis of 33
  34. 34. simple circuit phasor domain, RF impedance matching, properties of waves,transmission media, micro strip lines, high frequency parameters, formulationof S-parameters, properties, transmission matrix, generalized S-parameters.Passive Circuit design:Introduction, Smith chart, scales, applications of Smith chart, design ofmatching N/Ws, definition of impedance matching, matching using lumpedand distributed elements.Basic consideration in active N/Ws and design of amplifiers, oscillators,and detectors:Stability considerations, gain considerations, noise considerations. Linear andnon linear design, introduction, types of amplifiers, design of different typesof amplifiers, multi stage small signal amplifiers, design of transistoroscillators, detector losses, detector design.Mixers, phase shifters and RF and Microwave IC design:Mixer types, conversion loss for SSB mixers, one diode mixer, phase shifters,digital phase shifters, semiconductor phase shifters, RF and microwave ICdesign, MICs, MIC materials, types of MICs, hybrid vs monolithic ICs, chipmaterials.Text Book:Matthew. M. Radmanesh “RF and microwave electronics illustrated”,Pearson Edn Edition, 2004Ref Book:Reinhold Ludwig and pavel Bretchko “RF circuit design, theory andapplications”, Pearson Edn Edition, 2004 ADVANCES IN VLSI DESIGN Subject Code : 12EC009 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Review of MOS Circuits: MOS and CMOS static plots, switches,comparison between CMOS and BI - CMOS. 34
  35. 35. MESFETS: MESFET and MODFET operations, quantitative description ofMESFETS.MIS Structures and MOSFETS: MIS systems in equilibrium, under bias,small signal operation of MESFETS and MOSFETS.Short Channel Effects and Challenges to CMOS: Short channel effects,scaling theory, processing challenges to further CMOS miniaturizationBeyond CMOS: Evolutionary advances beyond CMOS, carbon Nano tubes,conventional vs. tactile computing, computing, molecular and biologicalcomputing Mole electronics-molecular Diode and diode- diode logic .Defecttolerant computing,Super Buffers, Bi-CMOS and Steering Logic: Introduction, RC delaylines, super buffers- An NMOS super buffer, tri state super buffer and paddrivers, CMOS super buffers, Dynamic ratio less inverters, large capacitiveloads, pass logic, designing of transistor logic, General functional blocks -NMOS and CMOS functional blocks.Special Circuit Layouts and Technology Mapping: Introduction, Talleycircuits, NAND-NAND, NOR- NOR, and AOI Logic, NMOS, CMOSMultiplexers, Barrel shifter, Wire routing and module lay out.System Design: CMOS design methods, structured design methods,Strategies encompassing hierarchy, regularity, modularity & locality, CMOSChip design Options, programmable logic, Programmable inter connect,programmable structure, Gate arrays standard cell approach, Full customDesign.Reference Books: 1.Kevin F Brrnnan “Introduction to Semi Conductor Device”, Cambridge publications 2.Eugene D Fabricius “Introduction to VLSI Design”, McGraw-Hill International publications 3.D.A Pucknell “Basic VLSI Design”, PHI Publication 4.Wayne Wolf, “Modern VLSI Design” Pearson Education, Second Edition , 2002 35
  36. 36. RF MEMS Subject Code : 12EC127 IA Marks : 50 No. of Lecture Hours /week : 04 Exam Hours : 03 Total no. of Lecture Hours : 52 Exam Marks : 100Review – Introduction to MEMS. Fabrication for MEMS, MEMStransducers and Actuators . Microsensing for MEMS, Materials forMEMS.(Ref.1, Chap.1)MEMS materials and fabrication techniques – Metals, Semiconductors,thin films, Materials for Polymer MEMS, Bulk Machining for silicon basedMEMS, Surface machining for Silicon based MEMS, Micro StereoLithography for Polymer MEMS.(Ref.1, Chap.2)RF MEMS Switches and micro – relays. Switch Parameters, Basics ofSwitching, Switches for RF and microwave Applications , Actuationmechanisms, micro relays and micro actuators, Dynamics of Switchoperation, MEMS Switch Design and design considerations. MEMSInductors and capacitors.(Ref.1, Chap.3 & 4)Micromachined RF Filters and Phase shifters. RF Filters, Modeling ofMechanical Filters, Micromachanical Filters, SAW filters – Basics, Designconsiderations. Bulk Acoustic Wave Filters, Micromachined Filters forMillimeter Wave frequencies. Micromacbined Phase Shifters, Types andLimitations, MEMS and Ferroelectric Phase shifters, Applications. (Ref.1,Chap.5 & 6)Micromachined transmission lines and components. MicromachinedTransmission Lines – Losses in Transmission lines, coplanar lines,Meicroshield and membrane supported lines, Microshield components,Micromachined waveguides, directional couplers and mixers, Resonators andFilters.(Ref.1, Chap.7)Micomachined antennas. Design, Fabrication and Measurements.Integration and Packaging for RF MEMS. Roles and types of Packages, FlipChip Techniques, Multichip module packaging and Wafer bonding,Reliability issues and Thermal issues. (Ref.1, Chap.8 & 9Reference Books: 1“RF MEMS” – V K Varadan, A Laktakia and K J Vinoy, John Wiley, 2003 Reprint 2.“RF MEMS Circuit Design” .J De Los Santos, Artech House, 2002 36
  37. 37. 3.“Transaction Level Modeling with System C”. TLM Concepts andApplications for Embedded Systems, by Frank Ghenassia,Springer, 20054“Networks on Chips: Technology and Tools”, LucaBenini and Giovanni De Micheli , Morgan KaufmannPublishers, 2006. 37

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