2. Why?
To improve performance and energy in a future
many-core processor, it is vital that the
interconnect technology is optimized.
2
3. Optical networks
silicon photonics is a promising new interconnect
technology with lower power, higher bandwidth
density, and shorter latencies.
3
5. Introduction
Low-latency high-bandwidth: How?
Packet-switched networks
Made of carefully engineered links
Represent a shared medium that is highly scalable
Provide enough bandwidth
But...
Communication infrastructure is the major power
consumer
Power dissipation budget limit will be achieved
5
6. Introduction
Photonic Technology
Photonic interconnection networks
Low power dissipation independent of capacity
Ultra-high throughput
Minimal access latencies
Why less power?
Once a photonic path is established, the data is
transmitted end to end without the need for
repeating, regeneration and buffering
6
7. Introduction
Photonic Technology
Is photonic technology cheap enough?
Since 2006, high-speed optical communications
directly between silicon die are possible at a price-
performance point competitive with traditional
electrical interconnects
7
9. Architecture Overview Phonotonic
NoC
Hybrid Approach
Photonic interconnection network
Transmits high-bandwidth messages
Electronic control network
Controls the photonic network with small control messages
9
10. Architecture Overview
Phonotonic NoC
Before transmitting a photonic message, an
electronic control packet (path-setup packet)
is routed in the electronic network
acquires and sets up a photonic path for the
message
Photonic message is transmitted without buffering
once the path is acquired
10
11. Architecture Overview
Photonic NoC
Main advantage of photonic paths is bit-rate
transparency
Photonic switches switch on or off once per
message
Energy dissipation does not depend on the bit-rate
whereas
Traditional CMOS routers switch with every bit of
transmitted data
11
12. Architecture Overview
Photonic NoC
Another advantage is low loss in optical
waveguides
Power dissipated on a photonic link is completely
independent of the transmission distance
No matter if 2 cores are 2mm or 2cm apart
12
13. Architecture Overview
Photonic NoC
2X2 photonic switching elements
Capable of switching messages in a sub nanosecond
switching time
Switches are arranged as a 2D matrix and
organized in groups of four
Each group is controlled by an electronic router to
construct a 4X4 switch
Convenient for planar 2D topologies such as mesh
and torus
13
14. Architecture Overview
Photonic NoC
Each node includes a network gateway to serve as
a photonic network interface
Electronic/Optical (E/O) and Optical/Electronic (O/E)
conversions
Clock synchronization and recovery
Serialization/deserialization
Wavelength division multiplexing is used at
network gateways to provide larger data capacity
Optical equivalent of using parallel wires
14
15. Architecture Overview
Life of a Packet on Photonic NoC
Write operation from a processor in Node A to a memory in
Node B
1. A path-setup packet is sent on the electronic control
network
Includes information on the destination address of Node B
and additional control information such as priority and flow
id
2. Path-setup packet is routed in the electronic control
network
Reserves the photonic switches along the path
At every router in the path, the next hop is decided
according to the routing algorithm used
3. Path-setup packet reaches the destination
Photonic path is reserved
A fast light pulse is sent on the photonic path from Node B
to Node A to indicate that the path is reserved
15
16. Architecture Overview
Life of a Packet on Photonic NoC
4. The photonic message starts from Node A follows
path from switch to switch until it reaches Node
B
5. Message transmission completed
6. Path-teardown packet is sent from Node B to
Node A on the electronic control network to
release the path
7. Photonic message is checked for errors and a
small acknowledgement packet is sent from
Node B to Node A on the electronic control
network
16
18. Analysis and Comparison
Power Dissipation
Case Study Setup
16-node CMP where each processor requires
BWpeak = 1024 Gb/s
BWavg = 800 Gb/s
Traffic driven by the processors is assumed to be
uniform
Both networks use a mesh topology and XY
dimension order routing
18
19. Analysis and Comparison
Power Dissipation
Reference Electronic Network
4X4 mesh, where each router is integrated in one
processor tile
PW=765W
Photonic Network
8X8 photonic mesh
256 photonic switching elements organized as 64
4X4 switches
PW=30W (96% less power dissipation)
19
21. Conclusion
The advantages of photonic medium
High transmission bandwidth
Low power consumption
Recent (i.e. since 2006) advances make photonic
technology practical for NoCs
Fabrication of silicon photonic devices
Integration of photonic devices in CMOS electronic
circuits
Next generation of NoCs will possibly use photonic
technology
21
22. References
On the Design of a Photonic Network-on-Chip
Assaf Shacham, Keren Bergman, Luca P. Carloni
First International Symposium on Networks-on-Chip (NOCS'07), pp. 53-64,
2007
Photonic Networks-on-Chip: Opportunities and Challenges
Michele Petracca, Keren Bergman, Luca P. Carloni
IEEE International Symposium on Circuits and Systems 2008 (ISCAS 2008),
pp. 2789-2792, May 2008
The Case for Low-Power Photonic Networks on Chip
Assaf Shacham, Keren Bergman, Luca P. Carloni
Proceedings of the 44th Annual Conference on Design Automation, pp. 132-
135, 2007
Maximizing GFLOPS-per-Watt: High-Bandwidth, Low Power Photonic
On-Chip Networks
Shacham, K Bergman, LP Carloni
IBM P=ac2 Conference, October 2006
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