This document describes the organization and operation of a linear select memory. It consists of basic memory cells made up of flip-flops with control circuitry. The memory cells are arranged in rows and columns and selected by a memory address register and decoder. During a read, the selected memory cells output their stored data. During a write, input data is written into the selected memory cells. While this allows storing data in multiple memory locations, the complexity of the memory cells and large decoder required for large memories is disadvantageous.

1. LINEAR SELECT MEMORY
ORGANIZATION
PRESENTED BY
GHOLAMREZA KAKAMANSHADI
PANJAB UNIVERSITY, CHD, INDIA
Aug,2014

2. • In any memory there must be a basic memory cell.
• A basic memory cell is consist of an RS Flip-Flop with
associated control circuitry.
• The binary cell has three line inputs and one output.
• The select input enables the cell for reading or writing
and the read/write input determines the cell operation
when it is selected.

3. Memory Cell Operation

4. Basic memory cell
S Q
Flip
Flop
R Q
Select
Input
Write
Output

5. Basic memory cell will be drawn as
S
I o
W
Note:
To use this cell in a memory
Technique Select cells by Memory address register
Method to control selected cells written into or read from

6. S R State of flip-flop after clock
( Q )
0 0 Unchanged
0 1 0
1 0 1
1 1 Not used
S R Q
0 1 0
1 0 1
Q=S
R S FLIP FLOP

7. Basic memory cell
S Q
R Q
Select
Input
Write
Output
If Write =1 & Select = 1
Write Input into Q
1
1
1
1
1
0
1
0
1

8. Basic memory cell
S Q
R Q
Select
Input
Write
Output
If Write =0 & Select=1
S=R=0 OUT= Q
We read from
0
0
1
1
0
1
0
0
1
1
1
1

9. S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
00
01
10
11
s
R
s
R
decoder
Data Input
MAR1
MAR2
Two flip-flop
in MAR
I1 I2 I3
Fig. A basic memory organization for
Linear select IC memory
Read
Write
Data OutputO1 O2 O3

10. Four address memory with 3 bits per word.
The MAR selects the memory cells (Flip-Flop) to be
read from or written into through a decoder which
selects three Flip-Flop for each address that can be
in the memory address register.

11. S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
00
01
10
11
s
R
s
R
decoder
MAR1
MAR2
Data Output
I1 I2 I3
O1 O2 O3
Read
Write
Bit 1 Bit 2 Bit 3
Word 1
Word 2
Word 3
Word 4

12. There are four words and each row of three
memory cells comprises a word.
At any given time the MAR selects a word in
memory.
If the READ line is a 1 , the contents of the three
cells in the selected word are READ out on the
O1, O2,O3 lines.
If the write line is a 1, the value on I1, I2, I3, are
read into the memory.

13. Example :
• If the second row in the memory contains 110
in the three memory cells and if MAR contains
01 , then the second out put line from the
decoder will be 1, and the input gates and
output gates to these three memory cells will
be selected.

14. • If the READ line is a 1, then the outputs from
the three memory cells in the second row will
be 110 to the AND gates at bottom of the fig.
So output of the memory will be 110

15. S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
00
01
10
11
s
R
s
R
decoder
MAR1
MAR2
Data Output
I1 I2 I3
O1 O2 O3
Read
Write
1 1 0
01
0
1
1
1
1 1 0

16. • If the write line is a 1 and the MAR again
contains 01, the second row of flip-flops will
have selected input. Then the input value on
I1,I2,I3, will be read into the flip-flops in the
second row.

17. S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
S
I o
W
00
01
10
11
s
R
s
R
decoder
MAR1
MAR2
Data Output
I1 I2 I3
O1 O2 O3
Read
Write
1 0 1
01
0
1
1
1
1 0 1

18. There is only one problem with the memory:
its complexity
The basic memory cell is complicated, and for
large memories the decoder will be large.

19. The End