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Introduction to IP Cores with Xilinx ISE 9.2 and Digilent Spartan 3E Starter Kit Board

Technology
1 of 19
Chandrajit Pal Mtech(I.T) A.K CHOUDHURY SCHOOL OF I.T UNIVERSITY OF CALCUTTA MAIL:palchandrajit@gmail.com
[object Object],[object Object],[object Object],[object Object],[object Object],Introduction to IP Cores with Xilinx ISE 9.2 and Digilent Spartan 3E Starter Kit Board
IP CORE( Intellectual Property ) ,[object Object],[object Object],[object Object]
Advantages and Disadvantages of IP CORES ,[object Object],[object Object],[object Object]
-Objective ,[object Object],[object Object],[object Object]
-Process ,[object Object],[object Object],[object Object]
-Implementation ,[object Object],[object Object],Fig. 1. New Source Wizard window
[object Object],[object Object],Fig. 2. First page of the LogiCore Window Fig. 3. Second page of the LogiCore Window
[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Steps(contd..
Click on the add_sub.vho file that was opened earlier in the project. Find the text which looks like this: ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Steps(contd..) ,[object Object],Table 1. Pin assignment for the adder_subtracter project.
You can check the pin assignment with Fig. 4 and Fig. 5: Fig. 4. Fig 5
Steps(contd…) In the figure below, a behavioral simulation is displayed of the adder-subtracter using Modelsim XE/III 6.2g [1]. When the input add is ‘0’ the system substracts a-b using 2’s complement otherwise, it adds a+b on the raising edege of the clock. Fig. 6. Behavioral simulation of the adder_subtracter project.
[object Object],Fig. 7. Leds associated to the output of the adder subtracter and the operation control SW3 included in the Digilent Spartan 3E Starter board.
References ,[object Object],[object Object],[object Object]
[object Object],YOU

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generate IP CORES

  • 1. Chandrajit Pal Mtech(I.T) A.K CHOUDHURY SCHOOL OF I.T UNIVERSITY OF CALCUTTA MAIL:palchandrajit@gmail.com
  • 2.
  • 3.
  • 4.
  • 5.
  • 6.
  • 7.
  • 8.
  • 9.
  • 10.
  • 11.
  • 12.
  • 13.
  • 14.
  • 15. You can check the pin assignment with Fig. 4 and Fig. 5: Fig. 4. Fig 5
  • 16. Steps(contd…) In the figure below, a behavioral simulation is displayed of the adder-subtracter using Modelsim XE/III 6.2g [1]. When the input add is ‘0’ the system substracts a-b using 2’s complement otherwise, it adds a+b on the raising edege of the clock. Fig. 6. Behavioral simulation of the adder_subtracter project.
  • 17.
  • 18.
  • 19.