Introduction: Field Programmable Gate Array #FPGA System on Chip #SoC #Nios_II_Processor Hard Processor System #HPS Advanced RISC Machine #ARM Logical bridges Share physical resources Related Works: Renovell et Al., testing #RAM modules in #FPGA Focus on functional tests RAM of the FPGA Wei et Al., RAM memory monitoring Embedded System from the #HardProcessor Wang et Al., Real-time applications Use memory optimized way during the execution of tasks based on SoC architecture real-time Electrocardiogram #ECG FPGA with two 8GB Dual Data Rate Synchronous Dynamic Random Access Memories #DDR3 #SDRAM Results: As shown in Fig 12, the SRAM is working in the logical part executing several tasks and it is validated that as time passes the memory consumption increases. In addition, the writing times will depend on the amount of memory to be written and this varies according to the task that is being executed by the user or those that he has programmed in the Nios II. As for the DD3, it is executing the Linux OS as a basis and additionally, a size proportional to the size of the SRAM is reserved for the respective comparisons, so it is observed that it has a higher consumption and longer response times. It should be considered in this comparison that the DD3 in addition to running the OS, also has the web server implemented which consumption varies according to the clients that are connecting to the webpage where it can be seen the memory monitoring of the embedded system. Also, thanks to the part of the HPS it is possible to monitor the memory of the embedded system without affecting its consumption. As shown in Fig. 13, the SRAM is not under the same workload since it is only responsible for storing what Nios II needs for the execution of the tasks. Finally, it was consider that the HPS portion to be very important for a clean monitoring not only of the SRAM but also of any core that is implemented in the FPGA portion, since if this application is implemented on a chip that only has FPGA the application would affect the consumption and performance of it, therefore you could not have completely reliable results.

1. Monitoring of system memory usage
embedded in FPGA
Víctor Asanza , Nathaly Sánchez, Rommel Saquicela and Luis Macas
Escuela Superior Politécnica del Litoral, ESPOL, Guayaquil, Ecuador
Facultad de Ingeniería en Electricidad y Computación, FIEC

2. Topics
• Introduction
• Related Works
• Methodology
• Results
• Discussion and Conclusions
Monitoring of system memory usage
embedded in FPGA

3. Introduction
• Field Programmable Gate Array (FPGA)
• System on Chip (SoC)
• Nios II Processor
• Hard Processor System (HPS)
• Advanced RISC Machine (ARM)
• Logical bridges
• Share physical resources

4. Related Works
• Renovell et Al., testing RAM modules in FPGA
• Focus on functional tests RAM of the FPGA
• Wei et Al., RAM memory monitoring
• Embedded System from the Hard Processor
• Wang et Al., Real-time applications
• Use memory optimized way during the
execution of tasks based on SoC architecture
• real-time Electrocardiogram (ECG)
• FPGA with two 8GB Dual Data Rate
Synchronous Dynamic Random Access
Memories (DDR3 SDRAM)

5. Methodology
Representation of communication between FPGA and HPS

6. Methodology
Flow chart of the Nios II process

7. Methodology
Process flow chart in Linux (HPS)

8. Results
Resources used of FPGA

9. Results
Average SRAM usage when executing tasks
Task Execution Time in SRAM

10. Results
Task usage percentage in DDR3Average Execution Time in DDR3

11. Discussion and Conclusions
Comparison in Usage of memory vs. Time Comparison of memory usage

12. For more information
Víctor Asanza
Mail: vasanza@espol.edu.ec
Facultad de Ingeniería en Electricidad y Computación, FIEC
Escuela Superior Politécnica del Litoral, ESPOL
Campus Gustavo Galindo Km 30.5 Vía Perimetral, P.O. Box 09-01-5863
090150 Guayaquil, Ecuador

13. Thank you!