Lab manual for Educational Purpose, Subject: VLSI Design

1. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 1
Lab Manual
Smt. Indira Gandhi College of Engineering,
Navi Mumbai
Department of Electronics and Telecommunication
Engineering
Subject: VLSI Design

2. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 2
Aim: Draw a layout of Resistive Load Inverter & CMOS Inverter using CMOS 0.12um
technology and simulate its transient characteristics.
CMOS 0.12um TECHNOLOGY using Microwind3
Draw diagram:

3. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 3
Output Simulation Waveforms:
Conclussion:

4. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 4
AIM: to Design CMOS Inverter
CMOS 0.12um TECHNOLOGY using Microwind3

5. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 5
Output Simulation Waveforms
Conclusion:

6. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 6
Aim: Draw a layout of CMOS NAND Gate using CMOS 0.12um technology and
simulate its transient characteristics.
CMOS 0.12um TECHNOLOGY using Microwind3

7. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 7
Output simulation waveform:
Conclussion:

8. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 8
Aim: To draw a layput of CMOS NOR gate using CMOS 0.12 um technology and
simulate its transient characteristics
CMOS 0.12um TECHNOLOGY using Microwind3

9. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 9
Output Simulation waveform:
Conclussion:

10. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 10
Aim : Draw a layout of CMOS Half Adder Gate using CMOS 0.12um
technology and simulate its transient characteristics.
CMOS 0.12um TECHNOLOGY using Microwind3

11. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 11
Simulation Waveforms:
Conclussion:

12. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 12
Aim : Draw a layout of CMOS Full Adder Gate using CMOS 0.12um
technology and simulate its transient characteristics.
CMOS 0.12um TECHNOLOGY using Microwind3

13. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 13
Simulation Waveforms
Conclussion:

14. VLSI DESIGN LAB MANUAL
FACULTY: UMAKANT B. GOHATRE, SIGCE, NAVI MUMBAI 14
Aim : Compare Transfer Characteristics of CMOS, Resistive Load and
NMOS Load Inverter.
CMOS 0.12um TECHNOLOGY using Microwind3