oro551

1. Unit 2:

2. Combinational Circuits
Output is function of input only
i.e. no feedback
When input changes, output may change (after a delay)
•
•
•
•
•
•
n inputs m outputs
Combinational
Circuits

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3. Combinational Circuits
Analysis
● Given a circuit, find out its function
● Function may be expressed as:
♦ Boolean function
♦ Truth table
Design
● Given a desired function, determine its circuit
● Function may be expressed as:
♦ Boolean function
♦ Truth table
A
B
C
A
B
C
A
B
A
C
B
C
F1
F2
?
?
?
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4. 3 / 65
Analysis Procedure
Boolean Expression Approach
A
B
C
A
B
C
A
B
A
C
B
C
F1
F2
ABC
A+B+C
AB+AC+BC
(A’+B’)(A’+C’)(B’+C’)
AB'C'+A'BC'+A'B'C
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC

5. A = 0
B = 0
C = 0
A = 0
B = 0
C = 0
A = 0
B = 0
A = 0
C = 0
B = 0
C = 0
F1
F2
Analysis Procedure
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Truth Table Approach A B C F1 F2
0 0 0 0 0
0
0
0
0
0
0
1
0
0

6. A = 0
B = 0
C = 1
A = 0
B = 0
C = 1
A = 0
B = 0
A = 0
C = 1
B = 0
C = 1
F1
F2
Analysis Procedure
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Truth Table Approach
0
1
0
0
0
0
1
1
1
A B C F1 F2
0 0 0 0 0
0 0 1 1 0

7. A = 0
B = 1
C = 0
A = 0
B = 1
C = 0
A = 0
B = 1
A = 0
C = 0
B = 1
C = 0
F1
F2
Analysis Procedure
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Truth Table Approach
0
1
0
0
0
0
1
1
1
A B C F1 F2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0

8. A = 0
B = 1
C = 1
A = 0
B = 1
C = 1
A = 0
B = 1
A = 0
C = 1
B = 1
C = 1
F1
F2
Analysis Procedure
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Truth Table Approach
0
1
0
0
1
1
0
0
0
A B C F1 F2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1

9. A = 1
B = 0
C = 0
A = 1
B = 0
C = 0
A = 1
B = 0
A = 1
C = 0
B = 0
C = 0
F1
F2
Analysis Procedure
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Truth Table Approach
0
1
0
0
0
0
1
1
1
A B C F1 F2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0

10. A = 1
B = 0
C = 1
A = 1
B = 0
C = 1
A = 1
B = 0
A = 1
C = 1
B = 0
C = 1
F1
F2
Analysis Procedure
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Truth Table Approach
0
1
0
1
0
1
0
0
0
A B C F1 F2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1

11. A = 1
B = 1
C = 0
A = 1
B = 1
C = 0
A = 1
B = 1
A = 1
C = 0
B = 1
C = 0
F1
F2
Analysis Procedure
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Truth Table Approach
0
1
1
0
0
1
0
0
0
A B C F1 F2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1

12. A = 1
B = 1
C = 1
A = 1
B = 1
C = 1
A = 1
B = 1
A = 1
C = 1
B = 1
C = 1
F1
F2
Analysis Procedure
Truth Table Approach
1
1
1
1
1
1
0
0
1
A B C F1 F2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
B
0 1 0 1
A 1 0 1 0
C
B
0 0 1 0
A 0 1 1 1
C
F1=AB'C'+A'BC'+A'B'C+ABC
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F2=AB+AC+BC

13. Design Procedure
Given a problem statement:
● Determine the number of inputs and outputs
● Derive the truth table
● Simplify the Boolean expression for each output
● Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3” code
 4-bits
 0-9 values
 4-bits
 Value+3
?
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14. Design Procedure
BCD-to-Excess 3 Converter
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
C
1 1 1
B
A
x x x x
1 1 x x
D
C
B
A
1 1 1
1
x x x x
1 x x
D
C
1 1
1 1
B
A
x x x x
1 x x
D
C
B
A
1 1
1 1
x x x x
1 x x
D
w =A+BC+BD
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x = B’C+B’D+BC’D’
y = C’D’+CD z = D’

15. Design Procedure
BCD-to-Excess 3 Converter
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
w
x = B’(C+D) + B(C+D)’ z = D’
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x
D
C
z
y
B
A
w = A+ B(C+D) y = (C+D)’+ CD

16. 15 / 65
Seven-Segment Decoder
a
b
c
g
e
d
f
?
w
x
y
z
a
b
c
d
e
f
g
w x y z a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1 0 1 0 x x x x x x x
1 0 1 1 x x x x x x x
1 1 0 0 x x x x x x x
1 1 0 1 x x x x x x x
1 1 1 0 x x x x x x x
1 1 1 1 x x x x x x x
y
1 1 1
1 1 1
x
x x x x
w 1 1 x x
z
BCD code
a = w + y + xz + x’z’ b = . . .
c = . . .
d = . . .

17. Binary Adder
Half Adder
● Adds 1-bit plus 1-bit
● Produces Sum and Carry
HA
x
y
S
C
x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
x
+ y
───
C S
x
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y
S
C

18. Binary Adder
Full Adder
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry
x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
x
+ y
+ z
───
C S
FA
x
y
z
S
C
y
x
0 1 0 1
1 0 1 0
z
0 0 1 0
0 1 1 1
z
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
y
x
C = xy + xz + yz
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19. Binary Adder
Full Adder
x
y
z
S
C
x
y
z
x
y
z
x
y
z
x
y
z
x
y
x
z
y
z
x
y
z
x
y
x
z
y
z
x
y
z
S
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C
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
C = xy + xz + yz

20. Binary Adder
Full Adder
x
y
z
S
C
HA
x
y
z
HA S
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C

21. 20 / 65
Binary Adder
c c c
3 2 1
+ x3 x2 x1 x0
+ y3 y2 y1 y0
────────
Cy S3 S2 S1 S0
FA
x3 x2
FA
FA
FA
y3 y2
x1
y1
x0
y0
S3 S2 S1 S0
C4 C3 C2 C1
0
BinaryAdder
x3x2x1x0 y3y2y1y0
S3S2S1S0
C0
Cy
Carry
Propagate
Addition

22. 21 / 65
Binary Adder
Carry Propagate Adder
A3 A2 A1 A0 B3 B2 B1 B0
CPA
S3 S2 S1 S0
C0
Cy
A3 A2 A1 A0 B3 B2 B1 B0
CPA
S3 S2 S1 S0
C0
Cy
x3 x2 x1 x0
y3 y2 y1 y0
x7 x6 x5 x4
y7 y6 y5 y4
S3 S2 S1 S0
S7 S6 S5 S4
0

23. BCD Adder
4-bits plus 4-bits
Operands and Result: 0 to 9
+ x3 x2 x1 x0
+ y3 y2 y1 y0
────────
Cy S3 S2 S1 S0
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0
0 + 0 0 0 0 0 0 0 0 0 = 0 0 0 0 0 0
0 + 1 0 0 0 0 0 0 0 1 = 1 0 0 0 0 1
0 + 2 0 0 0 0 0 0 1 0 = 2 0 0 0 1 0
0 + 9 0 0 0 0 1 0 0 1 = 9 0 1 0 0 1
1 + 0 0 0 0 1 0 0 0 0 = 1 0 0 0 0 1
1 + 1 0 0 0 1 0 0 0 1 = 2 0 0 0 1 0
1 + 8 0 0 0 1 1 0 0 0 = 9 0 1 0 0 1
1 + 9 0 0 0 1 1 0 0 1 = A 0 1 0 1 0
2 + 0 0 0 1 0 0 0 0 0 = 2 0 0 0 1 0
9 + 9 1 0 0 1 1 0 0 1 = 12 1 0 0 1 0
Invalid Code
Wrong BCD Value
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0001 1000

24. BCD Adder
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value
9 + 0 1 0 0 1 0 0 0 0 = 9 0 1 0 0 1 0 0 0 0 1 0 0 1 = 9
9 + 1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16
9 + 2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17
9 + 3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18
9 + 4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19
9 + 5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20
9 + 6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21
9 + 7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22
9 + 8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23
9 + 9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24
+ 6
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









25. BCD Adder
Correct Binary Adder’s Output (+6)
● If the result is between ‘A’ and ‘F’
● If Cy = 1
S3 S2 S1 S0 Err
0 0 0 0 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
S1
S
3
1 1 1 1
1 1
2
S
S0
Err = S3 S2 + S3 S1
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26. BCD Adder
A3 A2 A1 A0 B3 B2 B1 B0
Binary Adder
S3 S2 S1 S0
Cy
A3 A2 A1 A0 B3 B2 B1 B0
Binary Adder
S3 S2 S1 S0
Cy
0 0
Ci 0
Ci 0
S3 S2 S1 S0
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Cy
x3 x2 x1 x0 y3 y2 y1 y0
Err

27. Binary Subtractor
Use 2’s complement with binary adder
● x – y = x + (-y) = x + y’ + 1
x3 x2 x1 x0 y3 y2 y1 y0
A3 A2 A1 A0 B3
Binary Adder
S3 S2 S1 S0
Cy
B2 B1 B0
Ci 1
F3 F2 F1 F0
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28. Binary Adder/Subtractor
A3 A2 A1 A0 B3
Binary Adder
S3 S2 S1 S0
B2 B1 B0
Ci
Cy
M
x3 x2 x1 x0 y3 y2 y1 y0
F3 F2 F1 F0
M: Control Signal (Mode)
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● M=0  F = x + y
● M=1  F = x – y

29. Overflow
Unsigned Binary Numbers
FA
x3 x2 x1
FA
FA
FA
y3 y2 y1
x0
y0
S3 S2 S1 S0
C4 C3 C2 C1
0
Carry
FA
x2 x1
FA
FA
FA
2’s Complement Numbers
x3
y3 y2 y1
x0
y0
S3 S2 S1 S0
C4 C3 C2 C1
0
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Overflow

30. Magnitude Comparator
Compare 4-bit number to 4-bit number
● 3 Outputs: < , = , >
● Expandable to more number of bits
Magnitude
Comparator
A<B A=B A>B
A3A2A1A0 B3B2B1B0
x3  A3 B3  A3 B3
x2  A2 B2  A2 B2
x1  A1 B1  A1 B1
x0  A0 B0  A0 B0
(A  B)  x3 x2 x1 x0
(A  B)  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
(A  B)  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
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31. Magnitude Comparator
A3
(A<B)
B3
A2
B2
A1
B1
A0
B0
(A>B)
(A=B)
x3
x2
x1
x0
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32. Magnitude Comparator
3 2 1 0
A A A A B3 B2 B1 B0
I(A>B)
I(A<B)
I Magnitude
(A=B)
Comparator
A<B A=B A>B
A<B A=B A>B
x3 x2 x1 x0
y3 y2 y1 y0
x7 x6 x5 x4
y7 y6 y5 y4
Magnitude
3 2 1 0
A A A A B3 B2 B1 B0
A<B A=B A>B
I(A>B)
I(A=B)
Comparator
I(A<B)
0
1
0
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33. Decoders
Extract “Information” from the code
Binary Decoder
● Example: 2-bit Binary Number
Binary
1
x 0
0 Decoder
x0
Only one
lamp will
turn on
1
0
0
0
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34. Decoders
2-to-4 Line Decoder
I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Binary
Decode
r
I1
I0
y3
y2
y1
y0
I1
I0
Y3
Y2
Y1
Y0
Y3  I1 I0
Y1  I1 I0
Y2  I1 I0
Y0  I1 I0
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35. Decoders
3-to-8 Line Decoder
Binary
Decode
r
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
I2
I1
I0
Y7
Y6
Y5
Y4
Y
Y2
Y1
Y0
2 1 0
 I I I
 I2 I1 I0
2 1 0
 I I I
 I2 I1 I0
3  I2 I1 I0
 I2 I1 I0
2 1 0
 I I I
 I2 I1 I0
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36. Decoders
“Enable” Control
Binary
Decode
r
I1
I0
E
Y3
Y2
Y1
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
I1
I0
E
Y3
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Y2
Y1
Y0

37. Decoders
Expansion
I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
I2 I1 I0
Binary
Decode
r
I0
I1
E Y0
Y3 Y7
Y2 Y6
Y1 Y5
Y4
Y3
Y2
Y1
Y0
Binary
Decode
r
I0
I1
E
Y3
Y2
Y1
Y0
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38. Decoders
Active-High / Active-Low
I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
I1 I0 Y3 Y2 Y1 Y0
0 0 1 1 1 0
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 1 1 1
Binary
Decode
r
I1
I0
Y3
Y2
Y1
Y0
I1
I0
Y3
Y2
Y1
Y0
Binary
Decode
r
I1
I0
Y3
Y2
Y1
Y0
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39. 38 / 65
Implementation Using Decoders
Each output is a minterm
All minterms are produced
Sum the required minterms
Example: Full Adder
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Binary
Decoder
x
y
z
S C

40. Implementation Using Decoders
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Binary
Decoder
x
y
z
S C
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Binary
Decoder
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x
y
z
S C

41. Encoders
Put “Information” into code
Binary Encoder
● Example: 4-to-2 Binary Encoder
x3 x2 x1 y1 y0
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
1 0 0 1 1
Binary
Encoder
y1
y0
x1
x2
x3
Only one
switch
should be
activated
at a time
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42. Encoders
Octal-to-Binary Encoder (8-to-3)
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
Binary
Encode
r
Y2
Y1
Y0
I7
I6
I5
I4
I3
I2
I1
I0
Y2  I7  I6  I5  I4
Y1  I7  I6  I3  I2
Y0  I7  I5  I3  I1
I
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7
I6
I5
I4
I3
I2
I1
I0
Y2
Y1
Y0

43. Priority Encoders
4-Input Priority Encoder
I3 I2 I1 I0 Y1 Y0 V
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1
Priority
Encode
r
V
Y
Y
1
0
I3
I2
I1
I0
I0
I3
I2
I1
Y1
Y0
V
0
1
V  I3  I2  I  I
Y0  I3  I2 I1
2
Y1  I3  I
Y1
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I2
I3
I1
1 1 1 1
1 1 1 1
1 1 1 1
I0

44. Encoder / Decoder Pairs
Y2
Y1
Y0
I7
I6
I5
I4
I3
I2
I
I
1
0
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Binary
Encoder
Binary
Decoder
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45. Multiplexers
MUX Y
I0
I1
I2
I3
S S
1 0
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
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46. 45 / 65
Multiplexers
2-to-1 MUX
4-to-1 MUX
Y
I0
I1
MUX
S
I1
I0
Y
MUX Y
I0
I1
I2
I3
S S
1 0
S
I0
I1
S1 S0
Y
I2
I3

47. 46 / 65
Multiplexers
Quad 2-to-1 MUX
Y
I0 MUX
I1 S
I0 MUX Y
I1 S
Y
I0 MUX
I1 S
I0 MUX Y
I1 S
x3
x2
x1
x
y3
y2
y1
0
y0
S
Y3
Y2
Y1
Y0
S E
A3
A2
A1
A0
B3
B2
B1
B0
MUX
A3
A2
A1
A0
S E
Y3
Y2
Y1
Y0
3
B
B2
B1
B0

48. 47 / 65
Multiplexers
Quad 2-to-1 MUX
Y3
Y2
Y1
Y0
S E
A3
A2
A1
A0
B3
B2
B1
B0
MUX
A3
A2
A1
A0
S E
Y3
Y2
Y1
Y0
B3
B2
B1
B0
Extra
Buffers

49. Implementation Using Multiplexers
MUX Y
I0
I1
I2
I3
S S
1 0
x y F
0 0 1
0 1 1
1 0 0
1 1 1
Example
F(x, y) = ∑(0, 1, 3)
x y
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F
1
1
0
1

50. Implementation Using Multiplexers
x y z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Example
F(x, y, z) = ∑(1, 2, 6, 7)
MUX Y
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I0
I1
I2
I3
I4
I5
I6
I7
S2 S1 S0
x y z
0
1
1
0
0
0
1
1
F

51. Implementation Using Multiplexers
MUX Y
I0
I1
I2
I3
S S
1 0
x y z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Example
F(x, y, z) = ∑(1, 2, 6, 7)
x y
F
F = z
F = z
z
z
0
1
F = 0
F = 1
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52. MUX Y
I0
I1
I2
I3
I4
I5
I6
I7
S S S
2 1 0
Implementation Using Multiplexers
A B C D F
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C
F
F = D
F = D
F = D
F = 0
D
D
D
0
0
D
1
1
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F = 0
F = D
F = 1
F = 1

53. 52 / 65
Y
I0
I1
I2
I3
I4
I5
I6
I7
S2 S1 S0
Multiplexer Expansion
8-to-1 MUX using Dual 4-to-1 MUX
MUX Y
I0
I1
I2
I3
S S
1 0
MUX Y
I0
I1
I2
I3
S1 S0
Y
I0
I1
MUX
S
1 0 0

54. DeMultiplexers
I
Y3
DeMUX
Y2
Y1
Y0
S1 S0
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
I
Y3
Y2
Y1
Y0
S0
S1
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55. Multiplexer / DeMultiplexer Pairs
Y
I7
I6
I5
I4
I3
I2
I1
I0
I
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
MUX DeMUX
S2 S1 S0 S2 S1 S0
x2 x1 x0
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y2 y1 y0
Synchronize

56. DeMultiplexers / Decoders
Binary
Decoder
I1
I0
E
Y3
Y2
Y1
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
I
Y3
DeMUX
Y2
Y1
Y0
S S
1 0
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
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57. Three-State Gates
Tri-State Buffer
Tri-State Inverter
A Y
C
C A Y
0 x Hi-Z
1 0 0
1 1 1
A Y
C
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58. Three-State Gates
A
Y
C
B
D
C D Y
0 0 Hi-Z
0 1 B
1 0 A
1 1 ?
NotAllowed
Y=
A
C
B
A. if C = 1
B. if C = 0
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59. Three-State Gates
I1
I0
Y
S1
I3
I2
Binary
Decode
r
I1
I0
E
Y3
Y2
Y1
Y0
S0
E
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60. Homework
4-2 Obtain the simplified Boolean expressions for output F
and G in terms of the input variables in the circuit:
A
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B
C
D
F
G

61. Homework
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4-3 For the circuit shown in the “Quad 2-to-1 MUX”:
(a) Write the Boolean functions for the four outputs
in terms of the input variables
(b) If the circuit is listed in a truth table, how many rows
and columns would there be in the truth table?
4-5 Design a combinational circuit with three inputs, x, y, and
z, and three outputs, A, B, and C. When the binary input
is 0, 1, 2, or 3, the binary output is one greater than the
input. When the binary input is 4, 5, 6, or 7, the binary
output is one less than the input.

62. Homework
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4-11 Design a 4-bit combinational circuit incrementer. (A
circuit that adds one to a 4-bit binary number.) The
circuit can be designed using four half-adders.
4-13 The adder-subtractor circuit has the following values for
mode input M and data inputs A and B. In each case,
determine the values of the four SUM outputs and the
carry C.
M A B
(a) 0 0111 0110
(b) 0 1000 1001
(c) 1 1100 1000
(d) 1 0101 1010
(e) 1 0000 0001

63. Homework
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4-27 A combinational circuit is specified by the following three
Boolean functions:
F1(A, B, C) = ∑(2, 4, 7)
F2(A, B, C) = ∑(0, 3)
F3(A, B, C) = ∑(0, 2, 3, 4, 7)
Implement the circuit with a decoder constructed with
NAND gates and NAND or AND gates connected to the
decoder outputs. Use a block diagram for the decoder.
Minimize the number of inputs in the external gates.

64. Homework
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4-28 A combinational circuit is defined by the following three
Boolean functions:
F1 = x’ y’ z’ + x z
F2 = x y’ z’ + x’ y
F3 = x’ y’ z + x y
Design the circuit with a decoder and external gates.
4-31 Construct a 16  1 multiplexer with two 8  1 and one
2  1 multiplexers. Use block diagrams.
4-32 Implement the following Boolean function with a
multiplexer:
F(A, B, C, D) = ∑(0, 1, 3, 4, 8, 9, 15)

65. Homework
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4-33 Implement a full adder with two 4  1 multiplexers:
4-35 Implement the following Boolean function with a 4  1
multiplexer and external gates. Connect inputs A and B to
the selection lines. The input requirements for the four
data lines will be a function of variables C and D. These
values are obtained by expressing F as a function of C and
D for each of the four cases when AB = 00, 01, 10, and 11.
These functions may have to be implemented with
external gates.
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)