The document discusses the structure and classification of channels in UMTS networks, including physical, transport and logical channels, and their mapping relationships. It also outlines the key steps in the cell search procedure used for network acquisition and synchronization, as well as an overview of the random access channel procedure.
This presentation discusses about the WCDMA air Interface used in 3G i.e. UMTS. This Radio Interface has great capability on which Third Generation of Mobile Communication is built, with backward compatibility.
This presentation discusses about the WCDMA air Interface used in 3G i.e. UMTS. This Radio Interface has great capability on which Third Generation of Mobile Communication is built, with backward compatibility.
REALIZATION OF TRANSMITTER AND RECEIVER ARCHITECTURE FOR DOWNLINK CHANNELS IN...VLSICS Design
Long Term Evolution (LTE), the next generation of radio technologies designed to increase the capacity and speed of mobile networks. The future communication systems require much higher peak rate for the air interface but very short processing delay. This paper mainly focuses on to improve the processing speed and capability and decrease the processing delay of the downlink channels using the parallel processing technique. This paper proposes Parallel Processing Architecture for both transmitter and receiver for Downlink channels in 3GPP-LTE. The Processing steps include Scrambling, Modulation, Layer mapping, Precoding and Mapping to the REs in transmitter side. Similarly demapping from the REs, Decoding and Detection, Delayer mapping and Descrambling in Receiver side. Simulation is performed by using modelsim and Implementation is achieved using Plan Ahead tool and virtex 5 FPGA.Implemented results are discussed in terms of RTL design, FPGA editor, power estimation and resource estimation.
This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from the degree of the polynomial generator. Last, we from which our parallel implementation is derived. In comparison with previous works, the new scheme is faster and more compact and is independent of the technology used in its realization. In our solution, the number of bits processed in parallel can be different have also developed high-level parametric codes that are capable of generating the circuits autonomously when only the polynomial is given.
REALIZATION OF TRANSMITTER AND RECEIVER ARCHITECTURE FOR DOWNLINK CHANNELS IN...VLSICS Design
Long Term Evolution (LTE), the next generation of radio technologies designed to increase the capacity and speed of mobile networks. The future communication systems require much higher peak rate for the air interface but very short processing delay. This paper mainly focuses on to improve the processing speed and capability and decrease the processing delay of the downlink channels using the parallel processing technique. This paper proposes Parallel Processing Architecture for both transmitter and receiver for Downlink channels in 3GPP-LTE. The Processing steps include Scrambling, Modulation, Layer mapping, Precoding and Mapping to the REs in transmitter side. Similarly demapping from the REs, Decoding and Detection, Delayer mapping and Descrambling in Receiver side. Simulation is performed by using modelsim and Implementation is achieved using Plan Ahead tool and virtex 5 FPGA.Implemented results are discussed in terms of RTL design, FPGA editor, power estimation and resource estimation.
This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from the degree of the polynomial generator. Last, we from which our parallel implementation is derived. In comparison with previous works, the new scheme is faster and more compact and is independent of the technology used in its realization. In our solution, the number of bits processed in parallel can be different have also developed high-level parametric codes that are capable of generating the circuits autonomously when only the polynomial is given.
5. Channel Type
Physical channel
Transport channel
Logical channel
Node B
RNC
Physical channel
Transport channel
Logical channel
UE
6. Concept of channel
PHY layer
MAC layer
RLC layer
Transport channel
Physical channel
Logical channel
L1
L2
7. Channel Type
Logical channels:
Describe what is transported (i.e., the information to be
transmitted)
Transport channels:
Describe how the logical channels are to be transmitted.
Physical channels:
Represent the “transmission media” providing the
platform through which the information is actually
transferred.
8. Protocol stack of the Uu interface
L3
control
control
control
control
Logical
Channels
Transport
Channels
C-plane signalling U-plane information
PHY
L2/MAC
L1
RLC
DC
Nt
GC
L2/RLC
MAC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
Duplication avoidance
UuS boundary
BMC
L2/BMC
control
PDCP
PDCP L2/PDCP
DC
Nt
GC
Radio
Bearers
RRC
9. Logical Channels
Control Channel (CCH) Broadcast Control Channel (BCCH)
Paging Control Channel (PCCH)
Dedicated Control Channel (DCCH)
Common Control Channel (CCCH)
Traffic Channel (TCH) Dedicated Traffic Channel (DTCH)
Common Traffic Channel (CTCH)
10. Transport Channel
Random Access Channel (RACH)
Broadcast Channel (BCH)
Paging Channel (PCH)
Forward Access Channel (FACH)
Common Packet Channel (CPCH)
Common Transport Channels
DedicatedTransportChannels
Downlink Shared Channel (DSCH)
Dedicated Channel (DCH)
11. Physical Channel
Dedicated Physical Channel (DPCH)
Physical Random Access Channel (PRACH)
Physical Common Packet Channel (PCPCH)
Uplink Physical Channels
Secondary Common Control Physical Channel (S-CCPCH)
Common Pilot Channel (CPICH)
Primary Common Control Physical Channel (P-CCPCH)
Synchronization Channel (SCH)
Physical Downlink Shared Channel (PDSCH)
Downlink Physical Channels
Acquisition Indication Channel (AICH)
Page Indication Channel (PICH)
Dedicated Physical Channel (DPCH)
16. Physical Channels(1)
The physical channel is in a 3-layer structure by
the time:
Superframe
One superframe lasts 720ms, and consists of 72 radio frames.
radio frame
One radio frame has a period of 10ms, and comprises 15
timeslots with the same length. Corresponding to 38400 chips,
it is a basic unit of the physical layer.
Timeslot
A timeslot is a unit composed of a bit domain, corresponding to
2560 chips. The bit number and structure of a timeslot depends
on the specific type of the physical channel.
17. Physical Channels(2)
The frame structure of the physical channels is shown:
Tslot #1 Tslot #2 Tslot #I Tslot #15
Ttimeslot= 2560 chip
Frame #0 Frame #1 Frame #I Frame #71
Tframe=10 ms
Tsuperframe=720 ms
18. Uplink physical channel
2 UL Dedicated physical channel (DPDCH and
DPCCH)
2 UL Common physical channel (PRACH and
PCPCH)
UL Common physical
channel
UL Dedicated physical
channel
Dedicated physical
Control channel DPCCH
Dedicated physical
data channel
DPDCH
Physical random
Access channel
PRACH
Physical common
Packet channel
PCPCH
20. PRACH
Physical Random Access Channel
PRACH consists preamble part and message part
Random access transmit 1or more 4096 chips length
preambles and 10ms or 20ms length message part.
Message part
Preamble
4096 chips 10 ms (one radio frame)
Preamble Preamble
Message part
Preamble
4096 chips 20 ms (two radio frames)
Preamble Preamble
PRACH transmitted structure
21. PRACH
Physical Random Access Channel
10ms message part is split into 15 timeslots, each timeslot consists
of 2560chips.
Each timeslot includes data part and control part. They are
transmitted in parallel .
Data part :SF=32~256 , control part: SF=256.
Pilot
Npilot bits
Data
Ndata bits
Slot #0 Slot #1 Slot #i Slot #14
Tslot = 2560 chips, 10*2k
bits (k=0..3)
Message part radio frame T
RACH = 10 ms
Data
Control
TFCI
NTFCI bits
22. Downlink physical channel
DL physical channel include Dedicated physical channel、1 Shared
physical channel and five Common control channels.
DPCH
SCH
CPICH
PICH
AICH
CCPCH
PDSCH
DL common physical
channel
25. CPICH
There is 2 types of CPICH:P-CPICH and S-CPICH
P-CPICH:
P-CPICH of different cell uses the same Cch,256,0 OVSF code to
spread ,the bit rate of P-CPICH is also fixed.
The P-CPICH is scrambled by the primary scrambling code.
There is one and only P-CPICH per cell.
The P-CPICH is broadcast over the entire cell. it is used to search cell
primary
scrambling code during cell selection procedure. And it is also used
for measurement and estimation during handover, cell selection and cell
re-selection.
S-CPICH:
A arbitrary channelization code of SF=256 is used for the S-CPICH.
A S-CPICH is scrambled by either the primary or a secondary scrambling
code.
There may be 0,1 or several S-CPICH per cell.
A S-CPICH may be transmitted over the entire cell or part of the cell. It is
may be a phase reference for a dl DPCH, but it is decided by high layer
signalling.
27. SCH (1)
The Synchronization Channel (SCH) is a downlink signal
used for cell search.
The SCH consists of two sub channels, the Primary and
Secondary SCH.
The 10 ms radio frames of the Primary and Secondary
SCH are divided into 15 slots, each of length 2560 chips.
Structure of synchronization channel
28. SCH (2)
P-SCH
The Primary SCH consists of a modulated code of length
256 chips. The modulated code need not spreading and
scrambling.
The primary synchronization code (PSC) is transmitted once
every slot
The PSC is the same for every cell in the system.
S-SCH
The Secondary SCH consists of repeatedly transmitting a
length 15 sequence of modulated codes of length 256 chips.
the Secondary Synchronization Codes (SSC), transmitted in
parallel with the Primary SCH.
Each SSC is chosen from a set of 16 different codes of
length 256.
This sequence on the Secondary SCH indicates which of the
code groups the cell's downlink scrambling code belongs to.
32. Cell Search
UE has to get the system information before it
registers with the network and access to services.
The system information is beared in the BCH
channel, and its data is mapped into the Primary
CCPCH.
So the cell search procedure is mainly to decode
the data of P-CCPCH.
33. Cell search procedure (1)
The cell search is typically carried out in three
steps:
Step1: Slot synchronization
During the first step of the cell search procedure the UE
uses the SCH channel's primary synchronization code
to acquire slot synchronization to a cell.
This is typically done with a single matched filter (or any
similar device) matched to the primary synchronization
code which is common to all cells. The slot timing of the
cell can be obtained by detecting peaks in the matched
filter output.
35. Cell search procedure (2)
Step2: Frame synchronization and code-group
identification
During the second step of the cell search procedure, the
UE uses the SCH channel's secondary synchronization
code to find frame synchronization and identify the code
group of the cell found in the first step.
This is done by correlating the received signal with all
possible secondary synchronization code sequences,
and identifying the maximum correlation value. Since
the cyclic shifts of the sequences are unique the code
group as well as the frame synchronization is
determined.
38. Cell search procedure (3)
Step3: Scrambling-code identification
During the third and last step of the cell search
procedure, the UE determines the exact primary
scrambling code used by the cell.
The primary scrambling code is typically identified
through symbol-by-symbol correlation over the CPICH
with all codes within the code group identified in the
second step.
After the primary scrambling code has been
identified, the Primary CCPCH can be detected so
that the cell specific BCH information can be read.
40. Summary of the process
Channel
Synchronization
acquired
Note
Primary
SCH
Chip, Slot, Symbol
Synchronization
Synchronization 256 chips
The same in all cells
Secondary
SCH
Frame Synchronization,
Code Group
(one of 64)
15-code sequence of secondary
synchronization codes. There are 16
secondary synchronization codes. There
are 64 S-SCH sequences corresponding to
the 64 scrambling code groups 256 chips,
different for different cells and slot intervals
Common
Pilot CH
Scrambling code (one
of 8)
To find the primary scrambling code from
common pilot CH
PCCPCH Synchronization,
BCCH info
Fixed 30 kbps channel spreading factor 256
41. RACH procedure
UE decodes BCH to find out the available RACH sub-channels and
their scrambling codes and signatures
It selects randomly one of the available sub-channels and signatures
The downlink power is measured and the initial RACH power level is
set with a proper margin due to open loop inaccuracy
UE transmits 1 ms long preamble with the selected signature
Node B replies by repeating the preamble using Acquisition Indication
Channel (AICH)
UE decodes AICH message to see whether the NodeB has detected
the preamble
If AICH is not detected, the preamble is resend with 1 dB higher transmit
power
If AICH is detected, a 10 or 20 ms long message part is transmitted with
the same power as the last preamble
43. Exercise
pls write down the 3 types of channel and describe
their mapping relations.
One radio frame has a period of ( )ms, and
comprises( ) timeslots with the same length.
Corresponding to ( ) chips, it is a basic unit of
the physical layer.
pls describe the main function of each physical
channel.
pls describe the cell search procedure.
pls describe RACH procedure.