The document discusses hardware acceleration of the Burrows-Wheeler alignment algorithm. It describes how the algorithm works by creating a structure, examining occurrences of characters, and outputting the results. It notes that the algorithm is highly parallelizable. It then discusses different hardware accelerators like ASICs, GPUs, and FPGAs, noting that FPGAs provide flexibility, power efficiency, and can achieve a speed up of over 2x compared to CPUs. The goal is to implement the algorithm on an FPGA to align DNA reads faster and more efficiently than other platforms.

1. Hardware acceleration of the
Burrows-Wheeler Alignment
jessica.leoni@mail.polimi.it
riccardo1.cavadini@mail.polimi.it
guidowalter.didonato@mail.polimi.it
Jessica Leoni
Riccardo Cavadini
Guido Walter Di Donato

2. The Algorithm
Structure creation
Occurrences and locating
Output
Input
2

3. The Algorithm
Structure creation
Occurrences and locating
Output
Input
2

4. Parallelizable Matrix
When the character under exam is found in the
output, the correspondent value increases (+1)
3

5. a
Starting from the first line, looking for character ‘a’
3
Parallelizable Matrix

6. a
g
Does ‘a’ appear in the first position of the output?
3
Parallelizable Matrix

7. a
$
Does ‘a’ appear in the second position of the output?
3
Parallelizable Matrix

8. a
g
Does ‘a’ appear in the third position of the output?
3
Parallelizable Matrix

9. a
a
1
Does ‘a’ appear in the fourth position of the output?
3
Parallelizable Matrix

10. And something like this comes out
3
Parallelizable Matrix

11. Parallelization
•This is a highly parallelizable algorithm, and it has
been proved that a multi-threading process
speeds it up1
1 - Liu, Bo, Dixian Zhu, and Yadong Wang. "deBWT: parallel construction of Burrows–Wheeler Transform for large collection
of genomes with de Bruijn-branch encoding." Bioinformatics 32.12 (2016): i174-i182.
•The speedup is greater
as the number of
parallel threads grows,
but on CPU it saturates
at some point
4

12. Hardware Accelerators
Flexible
Power
efficient
Price
Speed up
achieved
ASICs
GPUs
FPGAs
5

13. Hardware Accelerators
Flexible
Power
efficient
Price
Speed up
achieved
ASICs
GPUs
FPGAs
5

14. Hardware Accelerators
Flexible
Power
efficient
Price
Speed up
achieved
ASICs
GPUs
FPGAs
5

15. So… Why FPGA?
• More reads aligned in less time,
compared to different CPU
platforms
2 - Xin, Yao, et al. "Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform."
Microelectronics Journal 44.8 (2013): 670-682.
• Fast, scalable and energy efficient
platform
• Final goal: on the Virtex-7, achieve
a speed up greater than 2x in
comparison to the Intel Xeon2
6

16. 2
2
Thank you for your attention!
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