1. What is Verification
• Act of proving or disproving the
correctness of a system with respect to
strict specifications regarding the system
• Process used to demonstrate functional
correctness of a design

2. Cost of Verification
• Can vary depending on form and method
of verification
• Also depends on what level of VLSI
realization it is conducted
Cost of verification [1]

3. Basic Idea
• Given specifications, does design do what
was specified
?

4. Forms of Verification
• Simulation: verify selected cases of
design functionality
• Formal: exhaustively verifies all behavior
of design
• Used a mix of specification justification
and functional demonstration

5. Component Verification
• During design phase each component
drawn up according to specification
• Specifications verified to meet
requirements
• Components to be exact replication of
architecture specification

6. Component Verification
• Each component separately simulated
• All input and output exhaustively tested
• Functions checked and errors corrected

7. Testbench
• A virtual environment used to verify the
correctness of a design
• Create a circuit that will provide input
stimuli for a design and check the output
response for proper function
CUT
TESTBENCH

8. Testbench
• Consists of four components:
– Input: stimuli needed for testbench to function
– Job: applies stimuli to model under test
– Check: retrieves output and analyzes
– Output: takes analysis and acts accordingly
• Not part of actual design

9. Memory Verification
• Used testbench to verify memory
component
• Marched through address space writing
and reading values to check function
Memory
TESTBENCH

10. CPU Verification
• Top level made up of every component
plus the needed signals to connect and
drive respective components
• Formal verification at this level not an
option

11. CPU Verification
• Test program to functionally verify all
possible CPU operations
• Each operation’s output was checked for
correctness
100100100011
000100111010
111000011111
000000011111
110000011111
111100000000
CPU

12. References
• 1. Dr. C. Stroud, ELEC 6970 Lecture 1
Auburn University, Fall 2006
• 2. Dr. V. Agrawal, ELEC 7770 Lecture 6
Auburn University, Spring 2007