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static const struct {
uint8_t value;
uint8_t mask;
const char* name;
int parameters;
void (*handler)(FDCtrl *fdctrl, int direction);
int direction;
} handlers[] = {
{ FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
{ FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
{ FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
…
};
if (fdctrl->data_pos == 0) {
/* Command */
pos = command_to_handler[value & 0xff];
FLOPPY_DPRINTF("%s commandn", handlers[pos].name);
fdctrl->data_len = handlers[pos].parameters + 1;
fdctrl->msr |= FD_MSR_CMDBUSY;
}
fdctrl->fifo[fdctrl->data_pos++] = value;
if (fdctrl->data_pos == fdctrl->data_len) {
/* We now have all parameters
* and will be able to treat the command
*/
…
pos = command_to_handler[fdctrl->fifo[0] & 0xff];
FLOPPY_DPRINTF("treat %s commandn", handlers[pos].name);
(*handlers[pos].handler)(fdctrl, handlers[pos].direction);
}
static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
{
FDrive *cur_drv = get_cur_drv(fdctrl);
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
timer_mod(fdctrl->result_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(get_ticks_per_sec() / 50));
}
static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
{
FDrive *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
fdctrl->fifo[0] = fdctrl->fifo[1];
fdctrl->fifo[2] = 0;
fdctrl->fifo[3] = 0;
fdctrl_set_fifo(fdctrl, 4);
} else {
fdctrl_reset_fifo(fdctrl);
}
} else if (fdctrl->data_len > 7) {
fdctrl->fifo[0] = 0x80 |
(cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
fdctrl_set_fifo(fdctrl, 1);
}
}
FD_CMD_READ_ID
result_timer
FD_CMD_READ_ID
FD_CMD_READ_ID
SRA SRB DOR TDR MSR DIR SRA SRB DOR TDR MSR DIR SRA SRB DOR TDR MSR DIR FIFO
FF C0 0C 00 80 80 FF C0 0C 00 90 80 FF C0 0C 00 D0 80 00 00 00 00 00 02 02 20.81
FF C0 0C 00 80 00 FF C0 0C 00 90 00 FF C0 0C 00 D0 00 40 05 01 00 00 01 02 20.32
FF C0 0C 00 80 00 FF C0 0C 00 80 00 FF C0 0C 00 D0 00 00 00 00 00 00 01 02 20.28
FF C0 0C 00 80 80 FF C0 0C 00 80 80 FF C0 0C 00 D0 80 00 00 00 00 00 01 02 20.29
FF FF 0C 20 80 7F FF FF 0C 20 D0 7F
FF FF 0C FF 80 00 FF FF 0C FF D0 00
FF FC 1C FF 80 FF FF FC 1C FF D0 FF
FF FF FF FF FF FF
FD_MSR_DIO
•
•
•
•
•
•
•
•
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Venom
Venom

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Venom

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  • 13. static const struct { uint8_t value; uint8_t mask; const char* name; int parameters; void (*handler)(FDCtrl *fdctrl, int direction); int direction; } handlers[] = { { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, … };
  • 14. if (fdctrl->data_pos == 0) { /* Command */ pos = command_to_handler[value & 0xff]; FLOPPY_DPRINTF("%s commandn", handlers[pos].name); fdctrl->data_len = handlers[pos].parameters + 1; fdctrl->msr |= FD_MSR_CMDBUSY; }
  • 15. fdctrl->fifo[fdctrl->data_pos++] = value; if (fdctrl->data_pos == fdctrl->data_len) { /* We now have all parameters * and will be able to treat the command */ … pos = command_to_handler[fdctrl->fifo[0] & 0xff]; FLOPPY_DPRINTF("treat %s commandn", handlers[pos].name); (*handlers[pos].handler)(fdctrl, handlers[pos].direction); }
  • 16. static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) { FDrive *cur_drv = get_cur_drv(fdctrl); cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50)); }
  • 17. static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) { FDrive *cur_drv = get_cur_drv(fdctrl); if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { fdctrl->fifo[0] = fdctrl->fifo[1]; fdctrl->fifo[2] = 0; fdctrl->fifo[3] = 0; fdctrl_set_fifo(fdctrl, 4); } else { fdctrl_reset_fifo(fdctrl); } } else if (fdctrl->data_len > 7) { fdctrl->fifo[0] = 0x80 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); fdctrl_set_fifo(fdctrl, 1); } }
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  • 20. FD_CMD_READ_ID SRA SRB DOR TDR MSR DIR SRA SRB DOR TDR MSR DIR SRA SRB DOR TDR MSR DIR FIFO FF C0 0C 00 80 80 FF C0 0C 00 90 80 FF C0 0C 00 D0 80 00 00 00 00 00 02 02 20.81 FF C0 0C 00 80 00 FF C0 0C 00 90 00 FF C0 0C 00 D0 00 40 05 01 00 00 01 02 20.32 FF C0 0C 00 80 00 FF C0 0C 00 80 00 FF C0 0C 00 D0 00 00 00 00 00 00 01 02 20.28 FF C0 0C 00 80 80 FF C0 0C 00 80 80 FF C0 0C 00 D0 80 00 00 00 00 00 01 02 20.29 FF FF 0C 20 80 7F FF FF 0C 20 D0 7F FF FF 0C FF 80 00 FF FF 0C FF D0 00 FF FC 1C FF 80 FF FF FC 1C FF D0 FF FF FF FF FF FF FF FD_MSR_DIO
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