Vamshi Krishna Boosam is an ASIC engineer with over 4 years of experience in ASIC verification and design. He has expertise in verification IP development using SystemVerilog and UVM methodologies. Some of his project experience includes verifying the MIPI-DPHY IP, developing test benches for the Dhanush WPU SOC, and verifying low power functionality at the gate level. He is proficient in SystemVerilog, C, UVM, and Perl scripting.

1. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
Objective
Consistently analyze and improve technical capabilities related to the field of
VLSI Technology there by increasing the efficiency and competitive with the fast
growing Technologies.
Summary of Skills
• Qualified ASIC Engineer with 4+ years of Experience in ASIC IP VERIFICATION, ASIC
DESIGN, and SOC LEVEL VERIFICATION with Excellent DEBUGGING Skills.
• Leveraged expertise in VERIFICATION IP DEVELOPMENT using SYSTEM VERILOG and
methodologies like UVM.
• Extensive experience in SOC LEVEL VERIFICATION using C BENCHES.
• Extensive experience in Validation (Dhanush-Advance, Dhanush-micro).
• Extensive Working Knowledge in Protocols like DFI, DDR3, LPDDR2, Policy Manager,
AHB, APB,MIPI-DPHY.
• High learning curve with the ability to embrace new protocols and technologies
with ease and to seamlessly integrate skill set into the project implementation
lifecycle.
• Good team player with excellent technical and interpersonal skills.
Education Qualifications
• B.Tech in Electronics and Communication Engineering, June 2010 with 70% from JNTU
University Hyderabad.
• Diploma in VLSI logic Design from VEDAIIT Hyderabad.
Work Experience:
• Currently Working for Inevecas as SR ASIC ENGINEER (contractor from Soctronics
Technologies) from Dec 2014 to till date.
• Currently Working for Ineda Systems as ASIC ENGINEER (contractor from Soctronics
Technologies) from October 2013 to Dec 2014.
• Worked for Soctronics Technologies as ASIC Engineer from November 2011 to October
2013.
Technical Expertise
Languages : System Verilog, C.
Verification Methodologies : UVM.
Scripting Languages : Perl, C-shell.
Simulators : Cadence IUS.
Protocols : AHB,APB,DFI-3.0,LPDDR2,DDR3,Fuse,
Policy Manager, Clocks, RTC,MIPI-DPHY.
.

2. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
• Project : MIPI-DPHY(JAN2015-Present)
Client : Invecas
Company : Soctronics pvt ltd
Team size : 3
Role : IP Verification
Description :
The MIPI-DPHY is a IP protocol, It complaints version 2.0 high speed serial
Interface.
Responsibilities :
• Developed bench for Tx-DPHY verification by using System verilog.
• Verified with DSI Mentor QVIP.
• Script for Automation.
• Documentation for verification environment.
• Automated bench for multi lane configuration.
• Verification for MIPI-CORE.
• Compatible bench development for three compilers(cadence,Questa,VCS)
• Project : Dhanush WPU SOC B0(Feb 2014 – Dec 2014)
Client : Ineda Systems
Company : Soctronics pvt ltd
Team size : 15

3. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
Role : IP Design, IP Verification, SOC
Verification.
Description :
The Dhanush WPU is an industry-first Wearable SOC that addresses all the
needs of the wearable device market. It features Hierarchical computing that
allows applications ad tasks to run at the right power optimized performance and
memory footprint and has an always-on sensor hub optimized for wearable devices.
Responsibilities :
• Dynamic Clock Gating Module Design
 Dynamic clock gating module design, which is used for clock gating for
slaves at idle time.
• ONOFF SUB ISLAND INTEGRATION
 ONOFF SUB island integration, which is one of the island in Dhanush.
 Linting for onoff sub subsystem.
• FUSE CONTROLLER VERIFICATION
 Developed the IP LEVEL BENCH for FUSE CONTROLLER using UVM.
 Coded Test cases to verify the functionality of FUSE CONROLLER in
various Aspects by using AHB Mentor VIP.
 Setup the COVERAGE MODEL to check CODE COVERAGE and FUNCTIONAL COVERAGE.
 Setup the MONITOR and SCOREBOARD to check the data integrity Between the
RTL and Bench.
 Checkers to check GF28SLP FUSE Control signal Timings.
 Developed a script for automation.
 Documented the TEST PLAN and VERIFICATION PLAN.
 Integrated in SoC level Bench.
• SENSOR CLOCKS SOC LEVEL VERIFICATION
 Code the SOC level Test Cases in C to Verify the SENSOR Clocks
functionally at SOC Level for Various Frequencies.
 Setup the System Verilog Bench to Support the C Test Cases.
 Checkers for All the clocks available in Sensor Subsystem to check
required frequencies are getting or not based on Programming.
 Documented the Test Plan.

4. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
• DHANUSH SOC CLOCKS SOC LEVEL VERIFICATION
 Code the SOC level Test Cases in C to Verify the DHANUSH SOC Clocks
functionally at SOC Level for Various Frequencies.
 Setup the System Verilog Bench to Support the C Test Cases.
 Checkers for All the clocks available in all Subsystem to check required
frequencies are getting or not based on Programming.
 Document the Test Plan.
• RTC SOC LEVEL VERIFICATION
 Code the SOC level Test Cases in C to Verify the RTC functionally at SOC
Level for Various Modes.
 Document the Test Plan.
• POLICY MANAGER SOC LEVEL VERIFICATION
 Code the SOC level Test Cases in C to Verify the POLICY MANAGER
functionally at SOC Level for Various Combinations.
 Policy manager is Controlled based on following IP’s
RTC,TIMER,UART,I2C,ADC,GPIO.
 Policy manger is heart of dhanush, which used for the ultra low power.
Based on RTC,TIMER,UART,I2C,ADC,GPIO sensor interrupts it will wake the
required Island followed with SENSOR ONOFF Island.
 Policy manager Control whole dhanush by making power/Clock disable to
idle Islands.
 Setup the System Verilog Bench to Support the C Test Cases.
 Checkers for All the tile resets, clocks in Sensor ONOFF,ONOFF SUB,BT-
BLE and TCM Subsystems to check Clocks are gating based on Policy
Control.
 Low Power RTL Verification for policy manager by inserting CPF.
 Document the Test Plan, Programming guide lines in Technical Reference
manual.

5. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
• BOOT ROM SOC LEVEL VERIFICATION
 Code the SOC level Test Cases in C to Verify the BOOT functionally at
SOC Level for Various Combinations of booting.
 Document the Test Plan.
• LOW POWER GATE LEVEL SIMULATION
 Developed a Gate level simulation setup.
 Verified all test scenarios of dhanush in Low power mode.
 Code C test cases for Low Power gate level simulation.
 Expert in Debugging Low power gate level simulation.
• VALIDATION
 Pre silicon validation for policy manager.
 Post silicon validation for policy manager, Low Power.
• DOCUMENTATION
 DHANUSH INFRA Document for SOC level verification environment.
Project : Dhanush WPU MICRO-B0 SOC(APR 2014 –AUG 2014)
Client : Ineda Systems
Company : Ineda Systems
Team size : 4

6. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
Role : SOC Verification
Description :
The Dhanush WPU is an industry-first Wearable SOC that addresses all the
needs of the wearable device market. It features Hierarchical computing that
allows applications and tasks to run at the right power optimized performance and
memory footprint and has an always-on sensor hub optimized for wearable devices.
• POLICY MANAGER SOC LEVEL VERIFICATION
 Code the SOC level Test Cases in C to Verify the POLICY MANAGER
functionally at SOC Level for Various Combinations.
 Verified latest changes and upgrades from the previous Dhanush WPU MICRO
 Policy manager is Controlled based on following IP’s
RTC,TIMER,UART,I2C,ADC,GPIO.
 Policy manager Control whole dhanush by making power/Clock disable to
idle Islands.
 Low Power RTL Verification for policy manager by inserting CPF.
 Low Power Gate level simulation for Dhanush WPU MICRO-B0 SOC.
• VALIDATION
 Pre silicon validation for policy manager.
 Post silicon validation for policy manager, Low Power.
Project : Dhanush WPU MICRO SOC(OCT 2013 –AUG 2014)
Client : Ineda Systems
Company : Ineda Systems
Team size : 4
Role : SOC Verification
Description :
The Dhanush WPU is an industry-first Wearable SOC that addresses all the
needs of the wearable device market. It features Hierarchical computing that
allows applications and tasks to run at the right power optimized performance and
memory footprint and has an always-on sensor hub optimized for wearable devices.
• IP’s verified in Soc level RTC,CLOCKS,SRAM.
• Fire-walk verification for dhanush-micro soc.

7. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
• POLICY MANAGER SOC LEVEL VERIFICATION
 Code the SOC level Test Cases in C to Verify the POLICY MANAGER
functionally at SOC Level for Various Combinations.
 Verified latest changes and upgrades from the previous Dhanush WPU MICRO
 Policy manager is Controlled based on following IP’s
RTC,TIMER,UART,I2C,ADC,GPIO.
 Policy manager Control whole dhanush by making power/Clock disable to
idle Islands.
 Low Power RTL Verification for policy manager by inserting CPF.
 Low Power Gate level simulation for Dhanush WPU MICRO SOC.
• VALIDATION
 Pre silicon validation for policy manager.
 Post silicon validation for policy manager, Low Power.
Project : DDR-PHY
Client : -
Company : Soctronics Technologies pvt ltd
Team size : 4
Role : IP Verification
Description :
Developed Models for MC,PHY,LPDDR2,DDR3 by using pure System Verilog.
In This we mainly focus on PHY, Here we developed to check the stand alone
functionality of PHY with Micron model.
• Developed MC model in System verilog to generate different scenarios on to
the DDR through PHY.
• Developed PHY model in System Verilog to send Information on to the DDR.
• Integrated MC-PHY-DDR.
• Assertions to check some of functionality of DFI.
• Monitor and scoreboard to check data from the MC to DDR are Correct.
• Integrated this environment in CRUX to check with JDEC.
• Developed monitor for to collect data from DDR.
• Developed Test case to generate random functionality on MC model.

8. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
• Verified all functionality of LPDDR2,DDR3.
• Coverage to MC DFI Interface.
• Perl Script for automation which do test case simulation generate report.
Project : ARIES
Client : -
Company : Soctronics Technologies pvt ltd
Team size : 4
Role : IP Verification
Description
ARIES is in-house project to place instead of licensed verification IP’s.
• SPI :
 Developed driver as part of spi-microwave type, sequences, register
sequences and test cases By using System verilog-UVM.
 Verified all the functionalities of spi.
 Coverage for SPI.
 Script to generate Test-cases based on sequence given as option to
this and it execute simulation command then it generate results of
that test case.
 Script to generate Sequence register library file to that IP.
• AHB :
 Developed Monitor AHB using System verilog-UVM it can handle 16 AHB
masters and 16 slaves.
 Developed Scoreboard to Check functionalities.
 Verified all the test scenarios on this monitor.
• APB :
 Developed model using UVM.
 To check functionalities of 1kb Register.
Profile Summary

9. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
I have experience on the Verification related to IP's like MIPI-DPHY,AHB, APB, LPDDR2, DFI,
I2C, Clocks, and experience on SOC verification like clocks, firewalk, rtc, sram, policy manager ,low power
gate simulation. Perl Scripting for automation. I have experience on debugging of SOC and IP level.
Other Information:
• I am conversant with English, Hindi, and Telugu
• My hobbies include Cooking, playing chess.
PERSONAL DETAILS:
• Father’s Name : Anjaneyulu Boosam
• DoB : 23-11-1989
• Present Address : Flat No.G2,Sai ganesh towers, puppalaguda, manikonda,
Hyderabad
• Permanent Address : 5-26,Madhapur,Twn:Nirmal,Dst:Adilabad – 504105
Declaration:
All the details furnished above are true to the best of my knowledge and belief.
Vamshi Krishna B.

10. Vamshi Krishna Boosam,
Mobile:+919885553862
Email:Vamshikrishna.boosam@gmail.com
I have experience on the Verification related to IP's like MIPI-DPHY,AHB, APB, LPDDR2, DFI,
I2C, Clocks, and experience on SOC verification like clocks, firewalk, rtc, sram, policy manager ,low power
gate simulation. Perl Scripting for automation. I have experience on debugging of SOC and IP level.
Other Information:
• I am conversant with English, Hindi, and Telugu
• My hobbies include Cooking, playing chess.
PERSONAL DETAILS:
• Father’s Name : Anjaneyulu Boosam
• DoB : 23-11-1989
• Present Address : Flat No.G2,Sai ganesh towers, puppalaguda, manikonda,
Hyderabad
• Permanent Address : 5-26,Madhapur,Twn:Nirmal,Dst:Adilabad – 504105
Declaration:
All the details furnished above are true to the best of my knowledge and belief.
Vamshi Krishna B.