1. A Wide-Band PLL-Based Frequency Synthesizer
with Adaptive Dynamics
Ping-Heng Wu, Ching-Yuan Yang, and So-Yu Chao
Department of Electrical Engineering, National Chung-Hsing University, Taichung, Taiwan
49262026@ee.nchu.edu.tw; ycy@nchu.edu.tw
Abstract— A wide tuning-range PLL-based frequency
synthesizer with constant damping factor ( ζ ) and natural
frequency ( ωn ) has been presented in this paper. This
synthesizer can be use for UHF and VHF channels. The lock
frequency range of the synthesizer can vary from several tens
MHz to 1.5 GHz with a 6-MHz channel, and the divide ratio of
the frequency divider operates from 5 to 300 precisely. The
synthesizer was simulated in 0.18-µm CMOS process with
6-MHz reference frequency and 350~500-KHz tunable
bandwidth, under a 1.8-V supply voltage.
I. Introduction
One difficulty in designing phase-locked loops (PLL)
for application-specific integrated circuits (ASIC) is to
provide ample flexibility for a wide variety of applications
such as DVB-T and DVB-H tuners [1]. To specify the UHF
and VHF operating frequencies at 48 ~ 480 MHz with a
step of 6 MHz, a wide-range synthesizer is presented in this
paper. Here, a self-biased technique is introduced to solve a
big problem about the parameters of damping factor ( ζ )
and natural frequency (ωn ) will varies with multiplication
factor N [2], [3], which may cause to effect the dynamic
performances of the system. Thus, the fixing ζ and ωn are
necessary.
II. SELF-BIASED FREQUENCY SYNTHESIZER
ARCHITECTURE
The architecture of the phase-locked loop (PLL) based
frequency synthesizer is shown in Fig.1. The main blocks
include a phase/frequency detector (PFD), a charge pump
(CP), a loop filter, a V-to-I converter, a programmable
frequency divider, and a current control oscillator (ICO). A
6-MHz reference (fref) is generated by an external crystal
oscillator.
A. The Self-biased Technique
The most difference from other self-biased synthesizer
[2][3] is the CP current is feedback controlled by VI
converter as shown in Fig. 1. As shown in equations (1) and
(2), the ICO tuning frequency is proportional to ICO control
current, and ICP is with fixed k multiply to Ictrl.
out ICO ctrl reff K I N f= ⋅ = ⋅ (1)
ref
CP ctrl
ICO
N f
I k I
K
⋅
= ⋅ = (2)
In addition, ωn and ζ can be found by:
2 2
ref mCP v
n
p p
k f GI K
C N C
ω
π π
⋅ ⋅⋅
= =
⋅ ⋅ ⋅
(3)
2 2 2 2
p p P ref mCP P v
R R k C f GI C K
N
ζ
π π
⋅ ⋅ ⋅⋅ ⋅
= =
⋅
(4)
where v m ICOK G K= ⋅ , pR and pC are loop filter parameters.
It is interesting to note that ωn and ζ are independent to
divider ratio N. Fig 2. is the simulation with Simulink under
the same ωn and ζ conditions.
B. Current-Control Oscillator (ICO) with Linear Voltage-
Control Resistor (VCR)
The characteristics of the oscillator can decide the
performance of the synthesizer, e.q., jitter, tuning range,
power dissipation, etc. In order to achieve wide tuning
range, we employ ring oscillator instead of LC tank
oscillator [4].
As shown in Fig. 3, the ICO is composed of four
differential current control delay cells with a replica circuit
shown in Fig. 4(a) [5]. The replica circuit is made up an
OPAMP with negative feedback and a copy of delay cell to
generate appropriate bias to a voltage-control resistor (VCR)
of Fig. 4(b). The fully differential delay cell has the VCR
load as Ron1.2 and a control current Iss. When Iss varies,
ICO’s oscillation frequency proportional to Iss follows
equation (5) [6]; VCR is the key element for delay cell
composed of Mp1, Mp2 and Mp3, because of its wide
Fig. 1 PLL frequency synthesizer architecture

2. dynamic range and linear characteristic, the output swing
held between Vdd to Vdd-Vref. Thanks to above techniques,
the ICO of the output swing is held constant and
independent of supply voltage, and can achieve wide linear
tuning range.
1,2
1
( )
ctrl
osc ctrl
on L L
I
f I
R C Vdd Vref C
∝ ∝ ∝
−
(5)
C. Wide Range Integer (N) Frequency Divider
Frequency Divider is an essential component in
synthesizer. Usually, the divider is based on dual-modulus
prescaler. To achieve wide divide ratio, it needs additional
counters, but the power dissipation and complex layout is
still a problem. Thus, we use a programmable divide-by-2/3
prescaler [7] as shown in Fig 5. As long as Modin = 0, the
prescaler divides 2. When Modin turns to 1, it divides 3 as p
= 1 and divide 2 as p = 0.
In Fig 6, the whole architecture consists of eight
divide-by-2/3 prescalers, a 3-to-8 MUX, and 12 OR gates,
all of them implement with MOS current mode logic
(MCML) because of its better EMC properties. The binary
control of P0 ~ P8 can determine division from 4 to 511,
and the 3-to-8 MUX selects the output Fout.
D .Current Match Charge Pump
The most serious problem of charge pump is its current
mismatch that generates phase offset and increases spur in
PLL [8]. In particular, it will reduce the lock range for this
work. To accomplish our wide locking range, an improved
scheme is shown in Fig 7. By using the OPAMP, as long as
the gain of the OPAMP is high enough, I1 = I2 = I4 when
“UP” ON, and I3 = I2 = I4 when “DN” ON. The size of
Mp2 and Mn4 should be optimized to minimize switching
time and turn on time. Mp6 and Mn7 are added to reduce
the charge coupling to gate and to enhance the switch time.
E. V to I Converter
Fig. 2 Simulation for changing N with the same ωn and ζ.
Fig. 3 Four-stage ring oscillator
Vref
Ictrl
Bias
Mn1 Mn2
Ron1 Ron2
(a) (b)
Fig. 4 (a) Replica bias of ICO and (b) VCR.
Fig. 5 Programmable divide-by-2/3 prescaler
Fig. 6 Wide-range divider architecture

3. VI converter plays a critical role in our work due to it
needs to convert the appropriate Ictrl to ICO and CP. The
scheme in Fig. 8 consists a source follower as level shifter,
and an OPAMP to enforce V- = V+. The value of Gm is
determined by v m ICOK G K= ⋅ . The essential of source
follower is to meet the CP current match range. Vb should
be optimized to ensure Mn2 in saturation and makes the
suitable voltage shift value from the loop filter.
F. The Loopfilter Design
The loopfilter parameters, including R1, R2, Cp and Cs,
are decision factor in synthesizer system. This filter in Fig.
9 is designed to have tunable bandwidth. These parameters
are determined in equations (3) and (4) with damping factor
and natural frequency assuming appropriate values.
III. SIMULATED RESULTS
This work was simulated in 0.18-µm CMOS process
under a 1.8-V supply voltage. The tunable loop-bandwidth
is 350KHz ~ 500KHz. The parameters in this synthesizer
are shown as Table 1 and they are verified with MATLAB
Simulink and HSPICE respectively. The parameters above
have been optimized to be easy integrated. The ICO’s linear
characteristic is a fatal condition to achieve ζ and ωn
independent to N. Fig 10 shows the almost perfect linear
tuning range of ICO can oscillator from around 100MHz to
1.5GHz. Another important characteristic may effect the
synthesizer’s performance is CP current match. Fig 11
shows the nearly perfect match CP current during charging
and discharging. Fig 12(a) and 12(b) are VI converter
simulation. In Fig12(a) the level shifter can shift down
voltage about 0.5v. Fig12(b) shows the voltage convert to
current performance. Fig 13(a) and Fig 13(b) are close loop
transient response for this system. In Fig. 13(a), we can note
that it locks at 50uA, i.e. at 90MHz, and in Fig13 (b), it lock
at 500uA, i.e., at 1.5GHz. One thing is obvious that they
have the same damping factor even vary N as behavior
simulation result in Fig 2.
Fig. 7 Charge pump
Fig. 8 V to I converter
Fig. 9 Second-order loopfilter
Fig. 10 Transfer characteristic of the VCO
Fig. 11 CP current match

4. Table 1 Design parameters
Cp 300pF
Cs 192pF
R1 30kΩ
R2 4kΩ
k 0.02
Gm 7.69×10−4
(I/V)
KICO 2.21×1012
(Hz/A)
IV. CONCLUSION
A self-biased wide band frequency synthesizer using in
UHF and VHF channels has been proposed in this work. A
brief concept for self-biased technique to achieve ζ and ωn
independent with multiplication N has been presented. The
technique with wide lock-in frequencies is also proposed.
ACKNOWLEDGMENT
The authors would like to thank National Chip
Implementation Center (CIC), Taiwan, for fabricating this
chip.
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(a) (b)
Fig. 12 VI converter simulation
(a) (b)
Fig. 13 PLL locked at (a) 90MHz and (b) 1.5GHz.
Table 2 Performance summary
Technology TSMC 0.18-µm 1P6M CMOS
Supply voltage 1.8±10%
Lock range of synthesizer <100MHz~1.5GHz
Tuning range of N 5~300
Frequency reference 6MHz
Bandwidth 350KHz~500KHz
Power consumption 60mW
Die size 1.4mm×1.4mm