The document describes control logic design for a PWM generator and SVPWM module. It outlines tasks to verify the ADC conversions, Clarke and Park transformations used in the control loop, speed measurement using resolver signals, safety and protection modules, flux and speed estimation, and closed-loop speed regulation. Test results are shown for varying voltage commands Vd and Vq with Ta, Tb, and Tc commands 120 degrees apart from the space vector. Waveforms are displayed with varying Vd commands and DC bus voltages.

1. Control Logic Design
PWM, ADC, Transformations and SVPWM generations and verification

2. Timeline

3. Code Explanation
1. ADC configuration section

4. 2. PWM generation

5. Transformations sections:

6. Log for display

7. Different tasks to be executed:
• Checking the ADC modules and SVPWM module.
• Verifying the ADC conversions and corresponding transformations- Clarke
and Park transformations used in the control loop.
• Verification of the speed measurement section using the revolver signals.
• Verification of the safety and protection modules.
• Flux and speed estimations used in the control loop.
• Verification of speed regulation by implementing the closed loop.

8. Test Results: Ta, Tb and Tc commands from the Space vector
Vd command=0.3
Vq command=0.3
Ta, Tb and Tc are 120deg apart

9. Changing the command Vd and Vq
Vd command=0.2-0.4
Vq command=0.2

10. DSO waveforms

11. Voltage extraction from DC bus voltage sensed
Vd=0.2, Vq=0.2
Vdc varying

12. Varying the Vd command
Vd=0.2-0.4 Vd=0.8
Vdc varying

13. Waveforms with varying Vd
Vd=0.1
Vd=0.2
Vd=0.4
Vd=0.6
Vd=0.75
Vd=0.85

14. Speed and Current Measurement Verification