1. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
Timing Requirements for SEl and clock signals
Mostafa Said Sayed
mostafa.Saied@ejust.edu.eg
June 4, 2013
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

2. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
1 Timing Requirements
SEL high period TH requirements
Clock edge requirements
2 Area problem
Critical value for DTSV
3 New Yield Formulations
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
4 Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

3. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
SEL high period TH requirements
Clock edge requirements
TH requirements
Assume that the delay of the transmission gate GT is tp
and the delay of the TSV is tTSV .
The SEL high period TH must maintain at 1 for at least tp to
catch the real value of V2.
Figure: TSV-BOX delays.Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

4. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
SEL high period TH requirements
Clock edge requirements
TH requirements - Cont.
Both SEL and Vo signals will encounter a delay tTSV
through the TSV to reach the top layer
Since tTSV delay is common in both signals therefore it will
not affect the operation of the DeMUX.
Vo will encounter another delay through the TG of the
DeMUX equal to tp also.
Therefore SEL must wait tp until Vo reaches DeMUX and
another tp until Vo passes through the TG of the DeMUX,
so now:
TH − tp ≥ tp, (1)
therefore:
TH ≥ 2tp. (2)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

5. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
SEL high period TH requirements
Clock edge requirements
TH requirements - Cont.
Figure: TH requirements.
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

6. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
SEL high period TH requirements
Clock edge requirements
Clock edge requirements.
Suppose that both V1 and V2 will be the inputs of two DFFs
with equal setup time tsu.
Since V2 is delayed with 2tp+tTSV , then the clock rising
edge for the DFF should rise at:
2tp + tTSV + tsu. (3)
But V1 is delayed with 2tp+tTSV +TH, so the clock rising
edge of the other DFF should rise at:
2tp + tTSV + tsu + TH. (4)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

7. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
SEL high period TH requirements
Clock edge requirements
Clock edge requirements - Cont.
Since there is one clock signal, then the clock of this layer
should have a rising edge at:
2tp + tTSV + tsu + TH, (5)
which will be suffice for both V1 and V2 to be read correctly
in both FFs.
Figure: Clock edge requirements.
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

8. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
Critical value for DTSV
When DTSV is small there may be no reduction in area
The critical or threshold value DTSVth
is the value at which
no reduction in area occurs
To determine the DTSVth
Let A1=A2
Then
Adie + NTSV ATSV = Adie +
NTSV
2
(ATSV + 2AMUX ) (6)
1
2
ATSV = AMUX − > ATSV = 2AMUX (7)
πr2
= 2AMUX (8)
r2
=
2AMUX
π
(9)
r =
DTSV
2
+ KOZavg =
2AMUX
π
(10)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

9. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
Critical value for DTSV
AMUX = 36 µm in TSMC 180 nm (11)
∴ DTSV + 2KOZavg = 9.654 µm (12)
∴ For area reduction DTSV + 2KOZavg ≥ 9.654 µm (13)
For DTSV =8 µm –> KOZavg=3.25 µm
8+6.5=14.5 > 9.654
∴ there will be area reduction
While for DTSV =5 µm –> KOZavg=0.75 µ
5+1.5=6.5 < 9.654
∴ there will be no area reduction
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

10. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
Critical value for DTSV
The solution for this problem is to decrease the MUX area
To decrease the MUX area, it must be implemented using
lower dimension technology that we do not have here in
EJUST
I am currently looking for a college that have TSMC 130
nm technology
The main problem is that area will affect also die yield and
cost (as will be seen later) since it’s conversely depends on
die area
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

11. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
Introduction
In [Cost-Effective Integration of Three-Dimensional (3D)
ICs Emphasizing Testing Cost Analysis] three kinds of
3D-IC yields have proposed
1 TSV yield YTSV
2 Die yield Ydie
3 Overall W2W yield YW2W
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

12. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
TSV yield YTSV
The TSV yield is the probability that all TSVs have no
defects.
Suppose that the probability for a faulty TSV is fTSV , then:
YTSV = Probability [all TSVs are non − faulty]
= (1 − fTSV )NTSV . (14)
The TSV yield of the traditional 3D-IC YTSV1
will be:
YTSV1
= (1 − fTSV )NTSV , (15)
The TSV yield of the 3D-IC with TSV-BOX YTSV2
:
YTSV2
= (1 − fTSV )
NTSV
2 . (16)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

13. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
TSV yield YTSV - Cont.
But since (1 − fTSV ) < 1, so:
YTSV2
> YTSV1
. (17)
According to the same reference fTSV varies from 50 ppm
to 5% in current TSV process technology.
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

14. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
Die yield Ydie
The die yield is modeled according to the distribution of the
random number of defects on the die.
It has been shown that the defects are usually not
randomly distributed across the chip, but are always
clustered. The widely used formula is the Gamma function
based yield model:
Ydie = (1 +
DoAdie
α
)−α
. (18)
The parameter α is a constant depends upon the
complexity of the manufacturing process, according to the
reference α is typically 2
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

15. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
Die yield Ydie - Cont.
Now we can determine the die yield before and after TSV
multiplexing, Ydie1
and Ydie2
respectively, therefore:
Ydie1
= (1 +
DoAdie1
α
)−α
, (19)
Ydie2
= (1 +
DoAdie2
α
)−α
. (20)
As stated from the previous equations, the die yield is
dependent on die area.
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

16. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
W2W overall yield YW2W
The overall yield of the 3D chip using W2W bonding can be
calculated as:
YW2W = [1 +
Do
α
(AdieN
+ ADFT )]−α
·
N−1
i=1
YS,W2W,i · (1 +
DoAdiei
α
)−α
, (21)
where ADFT is the area taken by the circuit of the DFT test,
and YS,W2W,i denotes the stacking yield between layer i
and layer i-1
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

17. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
W2W overall yield YW2W - Cont.
YS,W2W,i it is calculated as follows:
YS,W2W = Ybonding · YTSV , (22)
where Ybonding captures the yield loss of the chip due to
faults in the bonding processes and it’s independent of the
number of TSVs and YTSV is the TSV yield discussed
before.
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

18. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
W2W overall yield YW2W - Cont.
Three assumptions will be assumed to facilitate the
calculations of the overall yield:
1 Assume that there is no DFT test done to the chip therefore:
ADFT = 0. (23)
2 Let all the dies or layers to have the same area so,
Adie1
= Adie2
= · · · = AdieN
= Adie. (24)
3 Assume that the number of TSV per layer is the same then
we can say that
YS,W2W,1 = YS,W2W,2 = · · · = YS,W2W,N−1 = YS,W2W . (25)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

19. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
TSV yield YTSV
Die yield Ydie
W2W overall yield YW2W
W2W overall yield YW2W - Cont.
Now, Eq. 21 reduces to
YW2W = [1 +
DoAdie
α
]−Nα
· YN−1
S,W2W . (26)
As stated also in the equation above that YW2W also
dependent on die area
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

20. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
Introduction
In [Modeling the Economics of Testing: A DFT Perspective]
the die cost is
Ctest = Cprep + Cexec + Csilicon + Cquality (27)
Cprep captures fixed costs of test generation such as tester
program creation and nonrecurring costs.
Cexec consists of costs of test-related hardware such as
probe cards.
Csilicon is the cost required to incorporate DFT features
(here it will be zero).
Cquality is the cost increase mainly due to the fault dies that
pass the test while they are real faulty.
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

21. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(1)Preparation cost Cprep
The preparation cost is
Cprep =
(Ctest gen + Ctest prog + CDFT design)
Ydie
, (28)
Ctest gen is the test-pattern generation cost
Ctest prog is the tester-program preparation cost,
CDFT design is the additional design cost for DFT (will be set
to zero)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

22. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(1)Preparation cost Cprep - Cont.
Ctest gen = (Rperson hour Ttest gen)/V (29)
Ttest gen = Ktest gen · eAdie (30)
Ctest prog = βtest progCtest gen (31)
CDFT design = 0, assuming there is not DFT test (32)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

23. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(1)Preparation cost Cprep - Cont.
Parameter Description Range or value
Rperson hour Cost of one person-hour
for test generation $50/hr
Ttest gen Test generation time Ktest gen · eAdie .
V Production volume or the
total number of ICs produced from (105) to (108)
Ktest gen Constant multiplier that
relates test generation time
to the IC die area A 5122 hr
βtest prog A translating factor 0.20
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

24. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(2)Execution cost Cexec.
Cexec =
(Chw + Ctester )
Ydie
(33)
The cost per die of using hardware for testing (excluding the
tester) Chw is
Chw =
Qprobe V/Nprobe life
V
(34)
The cost per die of using the tester Ctester is
Ctester = [Ract + Rinact
(1 − βutil)
βutil
]Ttest (35)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

25. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(2)Execution cost Cexec. - Cont.
Where Ract is the cost rate (dollars per second) for an active
tester, Rinact is the cost rate for an inactive tester,
Ract = Rinact (1 + βact ) and Rinact =
(Qcapitalβdepr )
Tsec per yr
(36)
Qcapital = Kcapital · K
√
A
pins (37)
the tester utilization factor (the percentage of time the tester is
actually testing ICs) βutil is:
βutil = Ttest V/(Tsec per yr
Ttest V
Tsec per yr
) (38)
the average time(seconds) required to test a single IC Ttest is:
Ttest = Tsetup + [Ydie + βfail(1 − Ydie)]Kt timeA2
die (39)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

26. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(2)Execution cost Cexec. - Cont.
Parameter Description Range or value
Qprobe The unit price
of a probe card $1000
Nprobe life The number of ICs a probe
card can test 105 dies
Qcapital The tester price Eq. 37
Kcapital Tester price per pin $7,800/pin
Kpins Relates the number of pins to
the IC die area A 141/cm
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

27. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(2)Execution cost Cexec. - Cont.
Parameter Description Range or value
βdepr Depreciation rate 0.40
βact The fractional increase in rate
when a tester is actively used 0.25
βfail The average percentage of
good-die test time required
to test a defective IC not given
Tsetup The setup time for an IC
on the tester not given
Kt time a constant multiplier that relates
test time to IC die area A 4.8 s/cm2
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

28. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(3)Imperfect test quality Cquality.
Cquality = Closs perform + Cescape + Closs yield (40)
Closs perform is the loss in profit from performance
degradation because of added DFT circuitry (will be set to
0)
Cescape is the cost of test escape
Cescape = Mcost · αescape · Er (41)
where Er is the test escape rate
Er = 1 − Y1−f
die (42)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

29. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(3)Imperfect test quality Cquality. - Cont.
Mcost is the manufacturing cost
Mcost = Cbasic + Cfab (43)
where
Cbasic = Cprep + Cexec (44)
which is calculated before, and
Cfab =
Qwafer
πR2
wafer βwaf die
Adie
Ydie
(45)
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

30. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
(3)Imperfect test quality Cquality. - Cont.
Parameter Description Range or value
f Fault coverage 0.95 to 0.99
αescape the multiplying factor representing
the risk incurred by accepting
a defective IC as good 1 to 20
βwaf die the percentage of wafer area that
can be divided into dies 0.90
Qwafer wafer cost $1,300
Rwafer wafer radius 100 mm
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

31. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
(1)Preparation cost Cprep
(2)Execution cost Cprep
Conclusions about die cost
1 Cdie is not constant as was expected before
2 Cdie is dependent on die area Adie
3 To compute Cdie there are still 2 parameters that’s not
known yet which I do not find in that paper βfail and Tsetup
4 One way to find them is that, Fig. 2 in the paper draws the
Ttest , so we can pick up 2 points on the curve and solve
that 2 unknown linear system to find those unknowns
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals

32. Outline
Timing Requirements
Area problem
New Yield Formulations
Die Cost
The end
Thanks
Mostafa Said Sayed mostafa.Saied@ejust.edu.eg Timing Requirements for SEl and clock signals