The document is a lecture outline for a course on digital electronics, specifically focusing on successive approximation analog-to-digital converters (ADCs). It covers the working mechanism, components, advantages, and includes a quiz and assignment related to the topic. Teaching aids such as PPT, block diagrams, and model graphs are also mentioned to facilitate learning.

1. DEPARTMENT OF TECHNICAL EDUCATION
DEPARTMENT OF TECHNICAL EDUCATION
ANDHRA PRADESH
ANDHRA PRADESH
Name : Amarnath Katta
Designation : Lecturer
Branch : Electronics and Communication
Institute : GMR Polytechnic,Paderu,Vizag Dist.
Year/Semester : III-Semester
Subject : DIGITAL ELECTRONICS
Subject code : EE505
Topic : A/D and D/A converters
Duration : 150 Mts
Sub Topic : Successive Approximation ADC
Teaching Aids : PPT,Block Diagrams,Model graphs
1
EE505.73 TO 75

2. EE505.73 TO 75 2
OBJECTIVES
• On completion of this period ,you would be
able to know
• Successive Approximation ADC
a) Working
b) Advantages

3. Recap
• What is A/D conversation ?
• A/D converter using counter method.
3
EE505.73 TO 75

4. BLOCK DIAGRAM ADC (SAR type)
BLOCK DIAGRAM ADC (SAR type)
EE505.73 TO 75 4
VOLTAGE
COMPARATOR
SAR
4 BIT D/A
CONVERTER
BUFFER
REGISTER
Va
D0
D1
D2
D3
Vo
CONTROL
START
MSB
LSB
C
FIG (1)
VR

5. WORKING
WORKING
• Successive Approximation ADC consists of
1. Voltage comparator
2. SAR
3. D/A Converter
4. Control logic
5. Buffer register
EE505.73 TO 75 5

6. • VOLTAGE COMPARATOR:
Compares the voltage coming from DAC and analog input
voltage.
• D/A CONVERTER:
Converts digital signal to analog signal.
• SUCCESSIVE APPROXIMATION REGISTER :
SAR is a register where the output is ‘1000’ initially.
EE505.73 TO 75 6

7. CONTROL LOGIC:
Control logic sets or resets the SAR output depending on
the comparator output.
OUTPUT BUFFER:
Buffer register output provides the actual digital output.
EE505.73 TO 75 7

8. INITIAL SETTINGS
• Initially the SAR is set to ‘1000’.
• The DAC produces output V0 =
• Apply analog voltage as input to the comparator.
EE505.73 TO 75 8
2
R
V

9. WORKING
WORKING
• Control logic sets the MSB if the output of the comparator
is positive else it resets the MSB.
• Next lower significant bit is set to 1.
• Now DAC output is or .
• This process is continued till the LSB is checked
EE505.73 TO 75 9
4
3 R
V
4
R
V

10. ILLUSTRATION
EE505.73 TO 75 10
XXX
FIG (2)

11. • All the n-bits are determined after n cycles of V0 generation
and comparison with Va .
• Buffer register output provides the actual digital output.
• This binary output represents the value of the analog input.
• Thus an n-bit digital output is produced in ‘n’ clock cycles.
EE505.73 TO 75 11

12. ADVANTAGES
• Speed in operation.
• The conversion time is constant irrespective of analog input
• The number of clock pulses required for conversion is n.
EE505.73 TO 75 12

13. QUIZ
• The maximum number of clock pulses required
for conversion
a) 2N-1
b) n
c) 2N
d) 22N
EE505.73 TO 75 13

14. QUIZ
• Successive Approximation ADC is faster in operation
(TRUE/FALSE)
True
• Successive Approximation ADC requires D/A converter in
its circuit diagram. (TRUE/FALSE)
True
EE505.73 TO 75 14

15. Frequently asked questions
• Explain Successive Approximation ADC . (12M).
• What are the Advantages of Successive Approximation ADC
(4M)
EE505.73 TO 75 15

16. ASSIGNMENT
1. Explain Successive Approximation ADC.
2. What are the Advantages of Successive Approximation
ADC?
EC-304.73 TO 75 16