Stable rendering methods for Haptic interaction
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This document summarizes a study on stable haptic rendering methods using an FPGA. It discusses haptic interfaces and stability analysis, reviews the time domain passivity approach, and proposes new methods including a memory-based method and multi-rate TDPA method. Experimental results showed the multi-rate TDPA method achieved the best performance with the highest maximum virtual environment stiffness and least noise behavior, while the memory-based method had better performance than the conventional TDPA approach. Future work includes applying the methods to moving and time-varying virtual environments.
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web : http://www.lemenizinfotech.com/vlsi-ieee-projects-2016-2017/
Web : http://ieeemaster.com
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#Nios_II_Processor
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Advanced RISC Machine #ARM
Logical bridges
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Embedded System from the #HardProcessor
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⭐⭐⭐⭐⭐ CHARLA FIEC: Monitoring of system memory usage embedded in #FPGA
Introduction:
Field Programmable Gate Array #FPGA
System on Chip #SoC
#Nios_II_Processor
Hard Processor System #HPS
Advanced RISC Machine #ARM
Logical bridges
Share physical resources
Related Works:
Renovell et Al., testing #RAM modules in #FPGA
Focus on functional tests RAM of the FPGA
Wei et Al., RAM memory monitoring
Embedded System from the #HardProcessor
Wang et Al., Real-time applications
Use memory optimized way during the execution of tasks based on SoC architecture
real-time Electrocardiogram #ECG
FPGA with two 8GB Dual Data Rate Synchronous Dynamic Random Access Memories #DDR3 #SDRAM
Results:
As shown in Fig 12, the SRAM is working in the logical part executing several tasks and it is validated that as time passes the memory consumption increases. In addition, the writing times will depend on the amount of memory to be written and this varies according to the task that is being executed by the user or those that he has programmed in the Nios II.
As for the DD3, it is executing the Linux OS as a basis and additionally, a size proportional to the size of the SRAM is reserved for the respective comparisons, so it is observed that it has a higher consumption and longer response times. It should be considered in this comparison that the DD3 in addition to running the OS, also has the web server implemented which consumption varies according to the clients that are connecting to the webpage where it can be seen the memory monitoring of the embedded system. Also, thanks to the part of the HPS it is possible to monitor the memory of the embedded system without affecting its consumption.
As shown in Fig. 13, the SRAM is not under the same workload since it is only responsible for storing what Nios II needs for the execution of the tasks.
Finally, it was consider that the HPS portion to be very important for a clean monitoring not only of the SRAM but also of any core that is implemented in the FPGA portion, since if this application is implemented on a chip that only has FPGA the application would affect the consumption and performance of it, therefore you could not have completely reliable results.
Hao hsiang ma resume
Hao-Hsiang Ma is seeking a position in ASIC/VLSI/FPGA hardware design or verification. He has a Master's degree in Electrical and Computer Engineering from Rice University and previous degrees from National Cheng Kung University and Tamkang University in Taiwan. He has skills in Verilog, SystemVerilog, C/C++, and FPGA tools. His work experience includes internships at MediaTek doing verification and as a software engineer at FINDREAM. He has also completed projects involving linear equation solvers on FPGA boards, noise filtering, and cache coherence protocols.
Fitness Inheritance in Evolutionary and
Abstract—In evolutionary high-level synthesis, design solutions
have to be evaluated to extract information about some
figures of merit (such as performance, area, etc.) and to allow
the genetic algorithm to evolve and converge to Pareto-optimal
solutions. Since the execution time of such evaluations increases
with the complexity of the specification, this could lead to
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paper presents a model to exploit fitness inheritance in a multiobjective
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are based on a measure of distance between individuals and
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Resume_2017_Embedded
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Syllabus
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Introduction to objective, scope and outcome the subject
Chapter 2
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Chapter 3
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Linear Measurements: Instruments used. Linear Measurement by Tape, Ranging out Survey Lines and overcoming Obstructions; Measurements on sloping ground; Tape corrections, conventional symbols. Angular Measurements: Instruments used; Introduction to Compass Surveying, Bearings and Longitude & Latitude of a Line, Introduction to total station.
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Stable rendering methods for Haptic interaction
- 1. A STUDY ON STABLE HAPTIC RENDERING METHODS USING FPGA Student: Trung Hieu Do Advisor: Jee-Hwan Ryu BioRobotics Lab. School of ME - Korea University of Technology and Education
- 3. Haptic Interfaces & Stability Analysis
- 4. Overview of Haptic Interfaces Assumption: Virtual Objects are Static & Passive Master Device Human Operator Computer-based VE Slow update rate N. Diolaiti, G. Niemeyer, F. Barbagli, J. Kenneth Salisbury, Jr, ”Stability of Haptic Rendering: Discreatization, Quantization, Time-Delay and Coulomb Effects,” IEEE Transactions on Robotics , 22(2): pp. 256-268, April 2006. Human Operator Computer-based VE Slow update rate Embedded Haptic Controller Fast update rate 10-100 Hz 1-10kHz Master Device
- 5. Zero Order Hold & The Effect of Discretization Analog
- 6. Unstable Behavior of Haptic Interface
- 7. Review of the Time Domain Passivity Approach
- 9. Ideal Behavior of TPDA Method
- 10. Block Diagram Conventional TDPA method PO Update PO PC Clock signal Reset PO Conv. TDPA Stability Controller Update PC
- 11. Noisy Behavior of Conventional TDPA J-H. Ryu, B. Hannaford, D-S. Kwon, and J-H. Kim, “A Simulation/Experimental Study of the Noisy Behavior of the Time Domain Passivity Controller,” IEEE Trans. on Robotics , Vol. 21, No. 4, pp. 733-741.
- 12. Noisy Behavior of Conv. TDPA
- 14. Stable Behavior FPGA-based TDPA
- 15. Noisy Behavior in Stiffer VE
- 18. Block Diagram Memory-based Method Select Switch Data Address R/W Memory Direction Detector Memory-based method Stability Controller
- 19. Stable Behavior Memory-based Method
- 20. Slow Interaction Behavior Memory-based method
- 22. Multi-rate Haptic Computer-based VE 0.1kHz Multi-rate Haptic Controller 10kHz 10kHz sample rate Master device FPGA Human Operator Analog 0.1kHz sample rate
- 24. Behavior of Multi-rate Haptic Fm[N]
- 25. Activity of Multi-rate Haptic Interface Active period Passive period
- 26. Activity of Multi-rate Haptic Multi-rate haptic can’t guarantee Stability TDPA method Generated energy:
- 27. Multi-rate TDPA Computer-based VE 0.1kHz Multi-rate Force estimator 10kHz Time Domain Passivity Controller 10kHz Human Operator FPGA Master device
- 28. Block Diagram of Multi-rate TDPA FPGA-based Haptic Controller Force interpolator PC-based VE Down sample Encoder reader Multi-rate TDPA Stability Controller Conv.TDPA or event-based TDPA
- 29. Dissipitation of Generated Energy PC activated
- 30. Stability of Multi-rate TDPA
- 31. Slow Interaction of Multi-rate TDPA
- 33. Haptic System Human operator Motor driver Mechanical interface Master Device FPGA-Based Haptic Controller PC-based VE Physical interaction Virtual Interaction
- 35. Conclusions & Future Works
- 36. Maximum VE Stiffness VE
- 37. Conclusions Methods Features FPGA-based TDPA Memory-based Multi-rate TDPA Performance Worst performance Better performance Best performance Range of impedance Lowest max. stiffness Higher max.stiffness Highest max.stiffness Noise behavior Noise behavior Less noise behavior Least noise behavior Distortion (VE) When activity detected When releasing force higher than pressing force Interpolation& When activity detected Conservativeness No No Assumption of slowly change VE Update method Irregular update fast interupt Irregular update fast interupt Regular update Algorithm comlexity Simple Simplest Complicated Others Need high-speed RAM (Random access memory)
- 40. Implementation on High-Stiffness Moving Objects Master 1 Master 2 Passivate Object Virtual object
- 41. THANK YOU
Editor's Notes
- First of all, we have a review ... What is haptic interfaces and how is it constructed? includes of 3 main parts: PC-based VE, Human operator and Master device. Usually, VE is implemented inside a computer, using GPOS or RTOS (much more expensive) and with slow update rate. Master device is the physical interface with human operator, including the mechanical part and Electrical part
- Before coming to the Conclusions, we have a look at the Max. VE Stiffness graph What is Max. Stiffness? It indicates the Range of Impedance that haptic system can passively render. According to the graph,we can see the multi-rate TDPA has the widest range of Impedance, whille Conv. TDPA has the smallest. Beside, the higher VE frequency the higher stiffness allowed.