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SDAccel Design Contest: Intro Slide 1 SDAccel Design Contest: Intro Slide 2 SDAccel Design Contest: Intro Slide 3 SDAccel Design Contest: Intro Slide 4 SDAccel Design Contest: Intro Slide 5 SDAccel Design Contest: Intro Slide 6 SDAccel Design Contest: Intro Slide 7 SDAccel Design Contest: Intro Slide 8 SDAccel Design Contest: Intro Slide 9 SDAccel Design Contest: Intro Slide 10 SDAccel Design Contest: Intro Slide 11 SDAccel Design Contest: Intro Slide 12 SDAccel Design Contest: Intro Slide 13 SDAccel Design Contest: Intro Slide 14 SDAccel Design Contest: Intro Slide 15 SDAccel Design Contest: Intro Slide 16 SDAccel Design Contest: Intro Slide 17 SDAccel Design Contest: Intro Slide 18 SDAccel Design Contest: Intro Slide 19 SDAccel Design Contest: Intro Slide 20 SDAccel Design Contest: Intro Slide 21 SDAccel Design Contest: Intro Slide 22 SDAccel Design Contest: Intro Slide 23 SDAccel Design Contest: Intro Slide 24 SDAccel Design Contest: Intro Slide 25 SDAccel Design Contest: Intro Slide 26 SDAccel Design Contest: Intro Slide 27 SDAccel Design Contest: Intro Slide 28 SDAccel Design Contest: Intro Slide 29 SDAccel Design Contest: Intro Slide 30 SDAccel Design Contest: Intro Slide 31
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SDAccel Design Contest: Intro

  1. 1. Vivado/SDAccel Design Contest 11 Jan, 2018 Seminar Room @ DEIB Marco D. Santambrogio <marco.santambrogio@polimi.it> Politecnico di Milano
  2. 2. Project Example: Vivado/SDAccel Design Contest • Team: up to 2 members per entry/participation • Opening: 1.3 • Closing: 3.4 • Winners will be selected for – attending FPL@Dublin(Sept 2018) – (Joining NECST Group Conference @ San Francisco (22.5-2.6)) 3
  3. 3. Heterogeneous Complex Systems • Amazon EC2 F1 Instances – Xilinx UltraScale Plus FPGA – https://aws.amazon.com/about-aws/whats-new/2017/04/amazon-ec2-f1- instances-customizable-fpgas-for-hardware-acceleration-are-now-generally- available/ • IBM Power8 – Introducing the Coherent Accelerator Processor Interface (CAPI) port that is layered on top of PCI Express 3.0 – http://www-304.ibm.com/webapp/set2/sas/f/capi/home.html • OpenPower Foundation – http://openpowerfoundation.org/ • Microsoft Catapult – Stratix V (Arria 10 FPGA) – http://research.microsoft.com/en-us/projects/catapult/ • Ryft ONE – Big Data infrastructure due to an FPGA-accelerated architecture – http://www.ryft.com/ 4
  4. 4. Field-Programmable Gate Arrays • Configurable Logic Blocks – to implement combinational and sequential logic 6 CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB
  5. 5. LookUp Tables: LUTs • LUT contains Memory Cells to implement small logic functions • Each cell holds ‘0’ or ‘1’ . • Programmed with outputs of Truth Table • Inputs select content of one of the cells as output 7 O = f(D, C, B, A) OMUX BACD LUT 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
  6. 6. Field-Programmable Gate Arrays • Configurable Logic Blocks – to implement combinational and sequential logic • I/O blocks – special logic blocks at periphery of device for external connections 8 CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB
  7. 7. Field-Programmable Gate Arrays 9 • Configurable Logic Blocks – to implement combinational and sequential logic • I/O blocks – special logic blocks at periphery of device for external connections • Interconnections – wires to connect Inputs/Outputs to configurable logic blocks CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB
  8. 8. Xilinx FPGA and Configuration Memory 10 FPGA
  9. 9. Xilinx FPGA and Configuration Memory 11 Configuration Memory FPGA
  10. 10. Xilinx FPGA and Configuration Memory 12 Configuration Interfaces Configuration Memory FPGA
  11. 11. Xilinx FPGA and Configuration Memory 13 Configuration Interfaces Configuration bitstream Configuration Memory FPGA
  12. 12. 14 1010000 1111101 0100010100 1010100011 0101010111 1101010100
  13. 13. Reconfiguration in everyday life Football (Complete – Static) 15
  14. 14. 16 1010000 1111101 0100010100 1010100011 0101010111 1101010100
  15. 15. Reconfiguration in everyday life Soccer Football (Complete – Static) (Partial – Static) 17
  16. 16. 18 1010000 1111101 0100010100 1010100011 0101010111 1101010100 1010000 1111101
  17. 17. Reconfiguration in everyday life Soccer Football (Complete – Static) (Partial – Static) 19
  18. 18. 20
  19. 19. 22
  20. 20. 23
  21. 21. 12 January 2018 Marco D. Santambrogio/ Politecnico di Milano 24
  22. 22. Design flow 26 26
  23. 23. •ISE, RTL-based design entry with IP library Legacy •Microblaze, SDK, EDK Embedded CPU integration •Vivado HLS •SDNet (DSL PX) •Block stitching and manual integration in platform in RTL Raised abstraction for accelerators •SDSoC, SDNet, SDAccel •Predefined methods for data transfer & automated implementation Simplified host integration & automated infrastructure creation Time Abstraction 27 Innovation: Evolution of Design Environments
  24. 24. •ISE, RTL-based design entry with IP library Legacy •Microblaze, SDK, EDK Embedded CPU integration •Vivado HLS •SDNet (DSL PX) •Block stitching and manual integration in platform in RTL Raised abstraction for accelerators •SDSoC, SDNet, SDAccel •Predefined methods for data transfer & automated implementation Simplified host integration & automated infrastructure creation Time Abstraction 28 Innovation: Evolution of Design Environments
  25. 25. •ISE, RTL-based design entry with IP library Legacy •Microblaze, SDK, EDK Embedded CPU integration •Vivado HLS •SDNet (DSL PX) •Block stitching and manual integration in platform in RTL Raised abstraction for accelerators •SDSoC, SDNet, SDAccel •Predefined methods for data transfer & automated implementation Simplified host integration & automated infrastructure creation Time Abstraction 29 Innovation: Evolution of Design Environments
  26. 26. •ISE, RTL-based design entry with IP library Legacy •Microblaze, SDK, EDK Embedded CPU integration •Vivado HLS •SDNet (DSL PX) •Block stitching and manual integration in platform in RTL Raised abstraction for accelerators •SDSoC, SDNet, SDAccel •Predefined methods for data transfer & automated implementation Simplified host integration & automated infrastructure creation Time Abstraction 30 Innovation: Evolution of Design Environments
  27. 27. 31 Marco D. Santambrogio <marco.santambrogio@polimi.it> Politecnico di Milano

SDAccel Design Contest: Intro

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