SRAM for 1 bit storage elements We are making sram by n type access transistor but we replace n type transistor with p type transistor

1. A presentation on
4P2N SRAM
Under the guidance of
Dr. D. Vaithiyanathan
Department of Electronics and Communication
Engineering
National Institute of Technology, Delhi
Presented by:
Yogesh Pal (172221013)
M. Tech. (VLSI)

2. Objective
• 6T SRAM 4N2P suffers from some problem :
 Degradation in access speed
 Write margin
• DSC 4P2N 6T SRAM overcomes :
 Larger Cell Read Current
 Higher write margin

3. Introduction
SRAM is Combination of
Two inverters (INV1,INV2)
Two pass gate (WL)
Bit Lines (BL,BLB)
Mode of operation
Hold
Read
Write

4. Read Operation
1) Assume, initial
Q=1, Q_B=0
2) WL=1
3) BL,BL_B
pre-charge

5. Write Operation
1) Assume, Initial
Q=1 ,Q_B=0
2) WL=1
3) BL=0,
BL_B=1

6. Dual-Split-Controlled 4P2N SRAM
Large driving
capability due to pass
gate PMOS transistor
Higher P/N ratio
gives larger write
margin

7. Paper Worked
Figure : Write margin and Read signal to noise margin for 2N2P, 4P2N, DSC 4P2N
SRAM Cell at different voltages

8. Results

9. Reason for working on this paper
• Larger Icell current
• Higher write margin