This document discusses finite state machines (FSM) including Moore and Mealy machines. It provides examples of FSM implementations in VHDL including a vending machine FSM in both Moore and Mealy formats. The document contains slides on FSM concepts, definitions of Moore and Mealy machines, using FSM in VHDL with 3 processes, and examples of FSM for a scrambler mini project, string detector, and gumball vending machine. Practice problems and questions are provided at the end for the session material.
A sequential circuit is formed from a combinational circuit and storage elements. The circuit's state is defined by the information stored at any given time. The next state depends on the current inputs and state. A synchronous sequential circuit's behavior can be described at discrete time instances. It was designed as a Moore state machine to detect the "1101" sequence, with the output associated with the state. VHDL code implements it with a process changing the state variable based on the present state and input to determine the next state and output.
This document describes an experiment to implement a sequence detector using behavioral modeling. The sequence detector will output a 1 when it detects the input sequence of 11011. It includes the state transition diagram for detecting the 1011 sequence and the Verilog code for the sequence detector module. The code defines the different states like s0, s1, etc. and uses case statements to transition between the states based on the current input and update the output. The learning outcome is understanding how to detect a sequence step-by-step and learning Xilinx software commands.
This document discusses sequential circuits and their operation. It explains that sequential circuits have memory that stores the history of past inputs, and their outputs depend on both the current inputs and stored past inputs. The memory in sequential circuits is made up of flip-flops that are controlled by both combinational logic outputs and a clock signal. Sequential circuits can be described using state diagrams or state tables that define the next state and outputs based on the current state and inputs.
Computer Science and Engineering covers the basics of computers and C programming over 5 units. Unit 1 discusses fundamentals of computers including components, classifications, and number systems. Unit 2 covers algorithms, flowcharts, and pseudo code as well as the basics of the C programming language. Unit 3 discusses arrays and functions. Unit 4 focuses on strings and pointers. Unit 5 examines structures, unions, and file handling in C. The course aims to provide students with a foundation in computer fundamentals and an introduction to programming in C.
Actividades unidad vi educacion a distancia12200503ma
Este documento presenta actividades sobre comunicación, medios de comunicación y recursos didácticos en educación a distancia. Incluye definir conceptos de comunicación, elaborar un esquema de medios utilizados y un ensayo sobre la importancia educativa de la Web 2.0 y los sistemas de gestión de aprendizaje.
A sequential circuit is formed from a combinational circuit and storage elements. The circuit's state is defined by the information stored at any given time. The next state depends on the current inputs and state. A synchronous sequential circuit's behavior can be described at discrete time instances. It was designed as a Moore state machine to detect the "1101" sequence, with the output associated with the state. VHDL code implements it with a process changing the state variable based on the present state and input to determine the next state and output.
This document describes an experiment to implement a sequence detector using behavioral modeling. The sequence detector will output a 1 when it detects the input sequence of 11011. It includes the state transition diagram for detecting the 1011 sequence and the Verilog code for the sequence detector module. The code defines the different states like s0, s1, etc. and uses case statements to transition between the states based on the current input and update the output. The learning outcome is understanding how to detect a sequence step-by-step and learning Xilinx software commands.
This document discusses sequential circuits and their operation. It explains that sequential circuits have memory that stores the history of past inputs, and their outputs depend on both the current inputs and stored past inputs. The memory in sequential circuits is made up of flip-flops that are controlled by both combinational logic outputs and a clock signal. Sequential circuits can be described using state diagrams or state tables that define the next state and outputs based on the current state and inputs.
Computer Science and Engineering covers the basics of computers and C programming over 5 units. Unit 1 discusses fundamentals of computers including components, classifications, and number systems. Unit 2 covers algorithms, flowcharts, and pseudo code as well as the basics of the C programming language. Unit 3 discusses arrays and functions. Unit 4 focuses on strings and pointers. Unit 5 examines structures, unions, and file handling in C. The course aims to provide students with a foundation in computer fundamentals and an introduction to programming in C.
Actividades unidad vi educacion a distancia12200503ma
Este documento presenta actividades sobre comunicación, medios de comunicación y recursos didácticos en educación a distancia. Incluye definir conceptos de comunicación, elaborar un esquema de medios utilizados y un ensayo sobre la importancia educativa de la Web 2.0 y los sistemas de gestión de aprendizaje.
Healthy foods like fruits and vegetables provide health benefits and prevent obesity, while junk foods like chips and sweets can cause heart problems and obesity due to an unbalanced diet. The document lists common fruits like apples, pears, oranges and bananas and vegetables like kale, lettuce, broccoli and carrots as healthy options, with chips and chocolate identified as junk foods. The favorite food of the author is chips.
This document describes configuring VLANs on switches in a mesh network topology using Cisco Packet Tracer. VLANs are configured to separate devices into two VLANs ("Even" and "Odd") based on whether the last digit of their IP addresses is even or odd. The configuration involves creating the VLANs on each switch and assigning access ports to the appropriate VLAN based on the connected device's IP. Trunk ports are also configured between the switches to allow traffic from both VLANs to pass through the mesh network.
Paradigma keperawatan mencakup konsep manusia sebagai sistem holistik yang berinteraksi dengan lingkungannya, konsep keperawatan sebagai layanan kesehatan untuk mempromosikan kesehatan, dan konsep lingkungan fisik, psikologis, dan sosial yang mempengaruhi status kesehatan seseorang. Falsafah keperawatan penting sebagai pedoman bagi perawat dalam memberikan perawatan berdasarkan prinsip-prinsip kemanusiaan.
Este documento describe los problemas de disponibilidad y calidad del agua en la Región Lagunera de México, incluyendo niveles elevados de arsénico que ponen en riesgo la salud. Se presentan resultados de muestras de agua y alimentos que muestran contaminación por arsénico. También se discuten posibles efectos carcinogénicos y propuestas para preservar el derecho al agua potable, desarrollar conciencia sobre la calidad del agua, y aplicar un enfoque integral para resolver el problema a largo plazo.
Every day, a lot of people all over the world participate in games and sports activities or competitions.
Participation in sports improves physical fitness and overall health and wellness. Games and sports can
also result in injuries, some minor, some serious and still other in lifelong medical problem. Sports
injuries result from acute trauma or repetitive stress associated with athletic activities. Sports injuries can
affect bones or soft tissue (ligaments, muscles, tendons). There are numerous sports injuries happened in
the field of sports. It is very important for all coaches, trainers and players to know the causes symptoms,
prevention and treatment for all these common injuries in order to avoid most of these types of injuries,
This document discusses using Xilinx IP cores in FPGA design. It describes how to generate and customize IP cores using Xilinx tools, integrate the cores into VHDL designs, simulate designs using the ISIM simulator, and use language templates to easily insert code structures. The document provides guidance on each step of the IP core design flow from generation to simulation.
This document contains an evaluation test consisting of 50 multiple choice questions related to VHDL and digital logic design. It provides the questions, possible answer choices for each question, and a copyright notice at the bottom. The test is timed for 30 minutes and has a maximum score of 50 points. It was prepared by four individuals and last updated in October 2011.
This document provides an overview of sequential statements, loops, and other control structures in VHDL such as the for, while, next, exit, wait, null, and return statements. It includes examples of using these statements to implement counters, shift registers, and processes that wait for signals or time periods. The document also discusses functions and procedures in VHDL.
The document discusses VHDL coding techniques including designing first before coding, keeping data and controller blocks separate, keeping designs simple, coding what is understood, using generics to make code reusable, and reducing simulation time to efficiently debug designs. It also provides code examples for arithmetic circuits, data type conversions, and basic logic gates.
The document discusses VHDL structural description and generic statements. It provides examples of using components to build hierarchical designs by instantiating and interconnecting blocks. Generic statements allow creating reusable design units that can be configured for different uses by specifying generic parameters. The examples demonstrate how to build designs using structural description, instantiate components, and declare generics.
This document discusses different data types in VHDL including scalar, composite, and user defined types. Scalar types include enumerated types like bit, boolean, character, string, integer, floating point, and physical types. Composite types include arrays, which contain multiple elements of the same type, and records, which contain elements of different types. The document provides examples of how to declare different data types and use them in VHDL code. It also discusses predefined types like time and how to declare user defined types.
This document discusses data operators and attributes in VHDL. It describes concatenation and aggregate operators used to merge arrays and assign values. Examples show shifting and rotating registers using concatenation. Attributes allow returning information about entities, types, and signals like 'left, 'right, 'high, and 'length. The document contains exercises writing VHDL statements and an example using attributes to return values in a process. It also mentions using Modelsim to simulate sequential circuits with registered outputs appearing on the next clock cycle.
This document discusses concurrent statements in VHDL including assignment statements, processes, when-else statements, and with-select statements. It provides examples of how to use these statements to model concurrency and illustrates their usage by modeling a 4x1 multiplexer and 2x4 decoder. Key concepts covered include how processes allow sequential statements to be used concurrently, how signals are updated after processes suspend through transactions and events, and how multiple processes execute concurrently through the event scheduler advancing simulation time.
The document is a tutorial for using Xilinx ISE 10.1 software for synthesis and simulation of FPGA designs. It outlines the initial steps which include opening the software, setting preferences, creating a new project, adding VHDL files, checking syntax, and performing behavioral simulation. The tutorial explains how to view the design schematic after writing code, force inputs during simulation, and add cursors to view signal values at different times.
The key difference is that statements inside a process are executed sequentially, while statements outside a process (concurrent statements) are executed concurrently.
For the code snippets shown:
Left (inside process):
A will be assigned the value of C, because the assignments are executed sequentially - A is assigned B, then reassigned to C.
Right (outside process):
A will take on the value of both B and C concurrently, because the assignments are concurrent statements executed in parallel. This would result in a synthesis error.
So in summary, inside a process the statements are executed sequentially in the order written. Outside a process, statements execute concurrently and potentially cause conflicts.
The entity of system A would define the ports needed to interface system A to other external systems. Since system A is composed of systems B, C, and D, the entity of system A would define ports for:
- Interfacing with the outputs of systems B, C, and D
- Any other inputs needed by system A from external systems
- Any outputs of system A to external systems
The entity would define the direction (in, out, inout) and type (integer, bit, etc.) of each port.
For example (simplified):
entity system_A is
port(
B_out : in bit;
C_out : in bit;
D_out :
Healthy foods like fruits and vegetables provide health benefits and prevent obesity, while junk foods like chips and sweets can cause heart problems and obesity due to an unbalanced diet. The document lists common fruits like apples, pears, oranges and bananas and vegetables like kale, lettuce, broccoli and carrots as healthy options, with chips and chocolate identified as junk foods. The favorite food of the author is chips.
This document describes configuring VLANs on switches in a mesh network topology using Cisco Packet Tracer. VLANs are configured to separate devices into two VLANs ("Even" and "Odd") based on whether the last digit of their IP addresses is even or odd. The configuration involves creating the VLANs on each switch and assigning access ports to the appropriate VLAN based on the connected device's IP. Trunk ports are also configured between the switches to allow traffic from both VLANs to pass through the mesh network.
Paradigma keperawatan mencakup konsep manusia sebagai sistem holistik yang berinteraksi dengan lingkungannya, konsep keperawatan sebagai layanan kesehatan untuk mempromosikan kesehatan, dan konsep lingkungan fisik, psikologis, dan sosial yang mempengaruhi status kesehatan seseorang. Falsafah keperawatan penting sebagai pedoman bagi perawat dalam memberikan perawatan berdasarkan prinsip-prinsip kemanusiaan.
Este documento describe los problemas de disponibilidad y calidad del agua en la Región Lagunera de México, incluyendo niveles elevados de arsénico que ponen en riesgo la salud. Se presentan resultados de muestras de agua y alimentos que muestran contaminación por arsénico. También se discuten posibles efectos carcinogénicos y propuestas para preservar el derecho al agua potable, desarrollar conciencia sobre la calidad del agua, y aplicar un enfoque integral para resolver el problema a largo plazo.
Every day, a lot of people all over the world participate in games and sports activities or competitions.
Participation in sports improves physical fitness and overall health and wellness. Games and sports can
also result in injuries, some minor, some serious and still other in lifelong medical problem. Sports
injuries result from acute trauma or repetitive stress associated with athletic activities. Sports injuries can
affect bones or soft tissue (ligaments, muscles, tendons). There are numerous sports injuries happened in
the field of sports. It is very important for all coaches, trainers and players to know the causes symptoms,
prevention and treatment for all these common injuries in order to avoid most of these types of injuries,
This document discusses using Xilinx IP cores in FPGA design. It describes how to generate and customize IP cores using Xilinx tools, integrate the cores into VHDL designs, simulate designs using the ISIM simulator, and use language templates to easily insert code structures. The document provides guidance on each step of the IP core design flow from generation to simulation.
This document contains an evaluation test consisting of 50 multiple choice questions related to VHDL and digital logic design. It provides the questions, possible answer choices for each question, and a copyright notice at the bottom. The test is timed for 30 minutes and has a maximum score of 50 points. It was prepared by four individuals and last updated in October 2011.
This document provides an overview of sequential statements, loops, and other control structures in VHDL such as the for, while, next, exit, wait, null, and return statements. It includes examples of using these statements to implement counters, shift registers, and processes that wait for signals or time periods. The document also discusses functions and procedures in VHDL.
The document discusses VHDL coding techniques including designing first before coding, keeping data and controller blocks separate, keeping designs simple, coding what is understood, using generics to make code reusable, and reducing simulation time to efficiently debug designs. It also provides code examples for arithmetic circuits, data type conversions, and basic logic gates.
The document discusses VHDL structural description and generic statements. It provides examples of using components to build hierarchical designs by instantiating and interconnecting blocks. Generic statements allow creating reusable design units that can be configured for different uses by specifying generic parameters. The examples demonstrate how to build designs using structural description, instantiate components, and declare generics.
This document discusses different data types in VHDL including scalar, composite, and user defined types. Scalar types include enumerated types like bit, boolean, character, string, integer, floating point, and physical types. Composite types include arrays, which contain multiple elements of the same type, and records, which contain elements of different types. The document provides examples of how to declare different data types and use them in VHDL code. It also discusses predefined types like time and how to declare user defined types.
This document discusses data operators and attributes in VHDL. It describes concatenation and aggregate operators used to merge arrays and assign values. Examples show shifting and rotating registers using concatenation. Attributes allow returning information about entities, types, and signals like 'left, 'right, 'high, and 'length. The document contains exercises writing VHDL statements and an example using attributes to return values in a process. It also mentions using Modelsim to simulate sequential circuits with registered outputs appearing on the next clock cycle.
This document discusses concurrent statements in VHDL including assignment statements, processes, when-else statements, and with-select statements. It provides examples of how to use these statements to model concurrency and illustrates their usage by modeling a 4x1 multiplexer and 2x4 decoder. Key concepts covered include how processes allow sequential statements to be used concurrently, how signals are updated after processes suspend through transactions and events, and how multiple processes execute concurrently through the event scheduler advancing simulation time.
The document is a tutorial for using Xilinx ISE 10.1 software for synthesis and simulation of FPGA designs. It outlines the initial steps which include opening the software, setting preferences, creating a new project, adding VHDL files, checking syntax, and performing behavioral simulation. The tutorial explains how to view the design schematic after writing code, force inputs during simulation, and add cursors to view signal values at different times.
The key difference is that statements inside a process are executed sequentially, while statements outside a process (concurrent statements) are executed concurrently.
For the code snippets shown:
Left (inside process):
A will be assigned the value of C, because the assignments are executed sequentially - A is assigned B, then reassigned to C.
Right (outside process):
A will take on the value of both B and C concurrently, because the assignments are concurrent statements executed in parallel. This would result in a synthesis error.
So in summary, inside a process the statements are executed sequentially in the order written. Outside a process, statements execute concurrently and potentially cause conflicts.
The entity of system A would define the ports needed to interface system A to other external systems. Since system A is composed of systems B, C, and D, the entity of system A would define ports for:
- Interfacing with the outputs of systems B, C, and D
- Any other inputs needed by system A from external systems
- Any outputs of system A to external systems
The entity would define the direction (in, out, inout) and type (integer, bit, etc.) of each port.
For example (simplified):
entity system_A is
port(
B_out : in bit;
C_out : in bit;
D_out :
This document introduces a course on digital design using VHDL. The course will cover topics like VHDL statements, data types, finite state machines, and FPGA implementation. Each session will include illustrations, examples, exercises, labs, demos, assignments, and time for questions. Students will complete mini projects and a main project. Relevant materials and tools like Xilinx ISE, Modelsim, slides and guides will be provided. An attendance certification will be awarded upon completion.
This document introduces a course on digital design using VHDL. The course will cover topics like VHDL statements, data types, finite state machines, and FPGA implementation. Each session will include illustrations, examples, exercises, labs, demos, assignments, and time for questions. Students will complete mini projects and a main project. Relevant materials and tools like Xilinx ISE, Modelsim, slides and guides will be provided. An attendance certification will be awarded upon completion.
GraphSummit Singapore | The Art of the Possible with Graph - Q2 2024Neo4j
Neha Bajwa, Vice President of Product Marketing, Neo4j
Join us as we explore breakthrough innovations enabled by interconnected data and AI. Discover firsthand how organizations use relationships in data to uncover contextual insights and solve our most pressing challenges – from optimizing supply chains, detecting fraud, and improving customer experiences to accelerating drug discoveries.
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2024/06/building-and-scaling-ai-applications-with-the-nx-ai-manager-a-presentation-from-network-optix/
Robin van Emden, Senior Director of Data Science at Network Optix, presents the “Building and Scaling AI Applications with the Nx AI Manager,” tutorial at the May 2024 Embedded Vision Summit.
In this presentation, van Emden covers the basics of scaling edge AI solutions using the Nx tool kit. He emphasizes the process of developing AI models and deploying them globally. He also showcases the conversion of AI models and the creation of effective edge AI pipelines, with a focus on pre-processing, model conversion, selecting the appropriate inference engine for the target hardware and post-processing.
van Emden shows how Nx can simplify the developer’s life and facilitate a rapid transition from concept to production-ready applications.He provides valuable insights into developing scalable and efficient edge AI solutions, with a strong focus on practical implementation.
Essentials of Automations: The Art of Triggers and Actions in FMESafe Software
In this second installment of our Essentials of Automations webinar series, we’ll explore the landscape of triggers and actions, guiding you through the nuances of authoring and adapting workspaces for seamless automations. Gain an understanding of the full spectrum of triggers and actions available in FME, empowering you to enhance your workspaces for efficient automation.
We’ll kick things off by showcasing the most commonly used event-based triggers, introducing you to various automation workflows like manual triggers, schedules, directory watchers, and more. Plus, see how these elements play out in real scenarios.
Whether you’re tweaking your current setup or building from the ground up, this session will arm you with the tools and insights needed to transform your FME usage into a powerhouse of productivity. Join us to discover effective strategies that simplify complex processes, enhancing your productivity and transforming your data management practices with FME. Let’s turn complexity into clarity and make your workspaces work wonders!
Sudheer Mechineni, Head of Application Frameworks, Standard Chartered Bank
Discover how Standard Chartered Bank harnessed the power of Neo4j to transform complex data access challenges into a dynamic, scalable graph database solution. This keynote will cover their journey from initial adoption to deploying a fully automated, enterprise-grade causal cluster, highlighting key strategies for modelling organisational changes and ensuring robust disaster recovery. Learn how these innovations have not only enhanced Standard Chartered Bank’s data infrastructure but also positioned them as pioneers in the banking sector’s adoption of graph technology.
TrustArc Webinar - 2024 Global Privacy SurveyTrustArc
How does your privacy program stack up against your peers? What challenges are privacy teams tackling and prioritizing in 2024?
In the fifth annual Global Privacy Benchmarks Survey, we asked over 1,800 global privacy professionals and business executives to share their perspectives on the current state of privacy inside and outside of their organizations. This year’s report focused on emerging areas of importance for privacy and compliance professionals, including considerations and implications of Artificial Intelligence (AI) technologies, building brand trust, and different approaches for achieving higher privacy competence scores.
See how organizational priorities and strategic approaches to data security and privacy are evolving around the globe.
This webinar will review:
- The top 10 privacy insights from the fifth annual Global Privacy Benchmarks Survey
- The top challenges for privacy leaders, practitioners, and organizations in 2024
- Key themes to consider in developing and maintaining your privacy program
Communications Mining Series - Zero to Hero - Session 1DianaGray10
This session provides introduction to UiPath Communication Mining, importance and platform overview. You will acquire a good understand of the phases in Communication Mining as we go over the platform with you. Topics covered:
• Communication Mining Overview
• Why is it important?
• How can it help today’s business and the benefits
• Phases in Communication Mining
• Demo on Platform overview
• Q/A
Enchancing adoption of Open Source Libraries. A case study on Albumentations.AIVladimir Iglovikov, Ph.D.
Presented by Vladimir Iglovikov:
- https://www.linkedin.com/in/iglovikov/
- https://x.com/viglovikov
- https://www.instagram.com/ternaus/
This presentation delves into the journey of Albumentations.ai, a highly successful open-source library for data augmentation.
Created out of a necessity for superior performance in Kaggle competitions, Albumentations has grown to become a widely used tool among data scientists and machine learning practitioners.
This case study covers various aspects, including:
People: The contributors and community that have supported Albumentations.
Metrics: The success indicators such as downloads, daily active users, GitHub stars, and financial contributions.
Challenges: The hurdles in monetizing open-source projects and measuring user engagement.
Development Practices: Best practices for creating, maintaining, and scaling open-source libraries, including code hygiene, CI/CD, and fast iteration.
Community Building: Strategies for making adoption easy, iterating quickly, and fostering a vibrant, engaged community.
Marketing: Both online and offline marketing tactics, focusing on real, impactful interactions and collaborations.
Mental Health: Maintaining balance and not feeling pressured by user demands.
Key insights include the importance of automation, making the adoption process seamless, and leveraging offline interactions for marketing. The presentation also emphasizes the need for continuous small improvements and building a friendly, inclusive community that contributes to the project's growth.
Vladimir Iglovikov brings his extensive experience as a Kaggle Grandmaster, ex-Staff ML Engineer at Lyft, sharing valuable lessons and practical advice for anyone looking to enhance the adoption of their open-source projects.
Explore more about Albumentations and join the community at:
GitHub: https://github.com/albumentations-team/albumentations
Website: https://albumentations.ai/
LinkedIn: https://www.linkedin.com/company/100504475
Twitter: https://x.com/albumentations
Maruthi Prithivirajan, Head of ASEAN & IN Solution Architecture, Neo4j
Get an inside look at the latest Neo4j innovations that enable relationship-driven intelligence at scale. Learn more about the newest cloud integrations and product enhancements that make Neo4j an essential choice for developers building apps with interconnected data and generative AI.
“An Outlook of the Ongoing and Future Relationship between Blockchain Technologies and Process-aware Information Systems.” Invited talk at the joint workshop on Blockchain for Information Systems (BC4IS) and Blockchain for Trusted Data Sharing (B4TDS), co-located with with the 36th International Conference on Advanced Information Systems Engineering (CAiSE), 3 June 2024, Limassol, Cyprus.
Removing Uninteresting Bytes in Software FuzzingAftab Hussain
Imagine a world where software fuzzing, the process of mutating bytes in test seeds to uncover hidden and erroneous program behaviors, becomes faster and more effective. A lot depends on the initial seeds, which can significantly dictate the trajectory of a fuzzing campaign, particularly in terms of how long it takes to uncover interesting behaviour in your code. We introduce DIAR, a technique designed to speedup fuzzing campaigns by pinpointing and eliminating those uninteresting bytes in the seeds. Picture this: instead of wasting valuable resources on meaningless mutations in large, bloated seeds, DIAR removes the unnecessary bytes, streamlining the entire process.
In this work, we equipped AFL, a popular fuzzer, with DIAR and examined two critical Linux libraries -- Libxml's xmllint, a tool for parsing xml documents, and Binutil's readelf, an essential debugging and security analysis command-line tool used to display detailed information about ELF (Executable and Linkable Format). Our preliminary results show that AFL+DIAR does not only discover new paths more quickly but also achieves higher coverage overall. This work thus showcases how starting with lean and optimized seeds can lead to faster, more comprehensive fuzzing campaigns -- and DIAR helps you find such seeds.
- These are slides of the talk given at IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW 2022.
Dr. Sean Tan, Head of Data Science, Changi Airport Group
Discover how Changi Airport Group (CAG) leverages graph technologies and generative AI to revolutionize their search capabilities. This session delves into the unique search needs of CAG’s diverse passengers and customers, showcasing how graph data structures enhance the accuracy and relevance of AI-generated search results, mitigating the risk of “hallucinations” and improving the overall customer journey.
Pushing the limits of ePRTC: 100ns holdover for 100 daysAdtran
At WSTS 2024, Alon Stern explored the topic of parametric holdover and explained how recent research findings can be implemented in real-world PNT networks to achieve 100 nanoseconds of accuracy for up to 100 days.
How to Get CNIC Information System with Paksim Ga.pptxdanishmna97
Pakdata Cf is a groundbreaking system designed to streamline and facilitate access to CNIC information. This innovative platform leverages advanced technology to provide users with efficient and secure access to their CNIC details.
Building RAG with self-deployed Milvus vector database and Snowpark Container...Zilliz
This talk will give hands-on advice on building RAG applications with an open-source Milvus database deployed as a docker container. We will also introduce the integration of Milvus with Snowpark Container Services.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
Let's Integrate MuleSoft RPA, COMPOSER, APM with AWS IDP along with Slackshyamraj55
Discover the seamless integration of RPA (Robotic Process Automation), COMPOSER, and APM with AWS IDP enhanced with Slack notifications. Explore how these technologies converge to streamline workflows, optimize performance, and ensure secure access, all while leveraging the power of AWS IDP and real-time communication via Slack notifications.
Let's Integrate MuleSoft RPA, COMPOSER, APM with AWS IDP along with Slack
Session six
1. http://www.bized.co.uk
Session 6
Prepared by
Alaa Salah Shehata
Mahmoud A. M. Abd El Latif
Mohamed Mohamed Tala’t
Mohamed Salah Mahmoud
Version 02 – October 2011
Copyright 2006 – Biz/ed
2. http://www.bized.co.uk
Contents -Scrambler mini project discussion
-Finite State Machine
-What is FSM?
-Moore machine
6
-Mealy machine
-FSM in VHDL
2
Copyright 2006 – Biz/ed
5. Session 6
http://www.bized.co.uk
What is FSM
Any digital system consists of two part:
Data Part
Data part
Responsible for the processing of data. The Inputs Outputs
processing is done through some blocks such as (full
adder, digital filter, decoder,…)
Controls
Control part
Describes how and when these blocks will
communicate with each other.
The control part is generally described using a finite
Control Part
state machine.
5
Copyright 2006 – Biz/ed
6. Session 6
http://www.bized.co.uk
What is FSM
S1
Finite State Machine
FSM is simply a finite number of states that
S3 S2
each state describes a certain set of control
outputs that are connected to the data part
blocks.
The transition between these states depends
mainly on the inputs of the FSM.
There are two main types of FSM:
S4
Moore FSM
Mealy FSM
6
Copyright 2006 – Biz/ed
7. Session 6
http://www.bized.co.uk
FSM in VHDL
Assigning Moore Outputs
Output
Use a combinational ‘process’ to model Output Logic Logic
Outputs are only dependant on the current state
Assigning Mealy Outputs Outputs = f(State)
Use a combinatorial ‘process’ to model Output Logic
Outputs are dependant on the current state & the input Outputs = f(Inputs, State)
Output
Logic
7
Copyright 2006 – Biz/ed
8. Session 6
http://www.bized.co.uk
Moore FSM
In a Moore finite state machine, the output of
the circuit is dependent only on the state of
the machine and not on its inputs.
Inputs Next Present
state state Outputs
Next Machine Output
State State Logic
Logic Registers
8
Copyright 2006 – Biz/ed
9. Session 6
http://www.bized.co.uk
Mealy FSM
In a Mealy finite state machine, the output is
dependent both on the machine state as well
as on the inputs to the FSM.
Inputs Next Present
state state Outputs
Next Machine Output
State State Logic
Logic Registers
9
Copyright 2006 – Biz/ed
10. Session 6
http://www.bized.co.uk
Moore FSM transition
condition 1
state 1 state 2
transition
condition 2
Mealy FSM transition condition 1 /
output 1
state 1 state 2
transition condition 2 /
output 2
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Copyright 2006 – Biz/ed
12. Session 6
http://www.bized.co.uk
Moore FSM that Recognizes Sequence “10”
0 1
1 0
S0 / 0 S1 / 0 S2 / 1
reset
S0: No S1: “1” S2: “10”
Meaning elements observed observed
of states: of the
sequence
observed
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Copyright 2006 – Biz/ed
13. Session 6
http://www.bized.co.uk
Mealy FSM that Recognizes Sequence “10”
0/0 1/0 1/0
S0 S1
reset 0/1
S0: No S1: “1”
Meaning elements observed
of states: of the
sequence
observed
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Copyright 2006 – Biz/ed
15. Session 6
http://www.bized.co.uk
3-FSM in VHDL
-Finite State Machines Can Be Easily Described With Processes
-Synthesis Tools Understand FSM Description if Certain Rules Are Followed
-----State transitions should be described in a process sensitive to clock and asynchronous
reset signals only
-----Output function described using rules for combinational logic, i.e. as concurrent
statements or a process with all inputs in the sensitivity list
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Copyright 2006 – Biz/ed
16. Session 6
http://www.bized.co.uk
FSM in VHDL
The “3 Processes, 1 Clocked + separate transitions/actions” style
1-Process modeling “Next State Logic” Next
State
Logic
2-Process modeling "Current State Registers"
State
Registers
3-Process modeling “Output Logic”
Output
Logic
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Copyright 2006 – Biz/ed
17. Session 6
http://www.bized.co.uk
FSM in VHDL
Next-State Logic
Use a combinational ‘process’ to model next state logic
process ( current_state, <in1>, <in2>, <in3> … )
Begin
case ( Current_State ) is
when <state1> =>
Next
if ( <condition (<in1>, <in2>...)> ) then State
Next_State <= <state2>; Logic
elsif ( <condition (<in1>, <in2>...)> ) then
Next_State <= <state3>;
...
end process;
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Copyright 2006 – Biz/ed
18. Session 6
http://www.bized.co.uk
FSM in VHDL
Current-State
Use a sequential ‘process’ to describe current state logic*
Process (clock)
Begin
if rising_edge (clock) then
if ( reset = '1' ) then -- synchronous reset
Current_State <= <reset_state>;
else
Current_State <= Next_State; State
Registers
end if;
end if;
end process;
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Copyright 2006 – Biz/ed
20. Session 6
http://www.bized.co.uk
Vending Machine
Specifications
-Deliver package of gum after 15 piaster deposited
-Single coin slot for 5 and 10 piasters
Step 1 : Understand the problem
Draw a block diagram
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Copyright 2006 – Biz/ed
21. Session 6
http://www.bized.co.uk
Step 2 : Draw a state diagram
Reset
D S0 N
S6 S1
D N D N N = 5 piaster
S8 S7 S3 S2 D = 10 piaster
open open open D N
S5 S4
open open
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Copyright 2006 – Biz/ed
22. Session 6
http://www.bized.co.uk
Step 3 : State Minimization
Reset
S0
N
S1 D
N N = 5 piaster
D D = 10 piaster
S2
N,D
S3
open
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Copyright 2006 – Biz/ed
23. Session 6
http://www.bized.co.uk
Step 4
Write VHDL code (Moore)
Inputs and Outputs Reset
S0
library IEEE; N
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
S1 D
use IEEE.STD_LOGIC_UNSIGNED.ALL;
N
entity vend_machine_moore is D
Port (N : in STD_LOGIC; S2
D : in STD_LOGIC;
reset : in STD_LOGIC; N,D
clk : in STD_LOGIC; S3
tank_open : out STD_LOGIC);
end vend_machine_moore;
open
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Copyright 2006 – Biz/ed
24. Session 6
http://www.bized.co.uk
Define the states Reset
We need to define a new type for the names of the states
S0
N
S1 D
architecture Behavioral of vend_machine_moore is
N
type states is (s0,s1,s2,s3); D S2
signal n_state,p_state :states;
begin N,D
S3
open
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Copyright 2006 – Biz/ed
25. Session 6
http://www.bized.co.uk
The transition process Reset
Responsible for the transition of states from present state to next state.
S0
N
transition :process(clk,reset) S1 D
begin
if reset='1' then N
p_state <=s0 ; D
elsif rising_edge(clk) then S2
p_state <= n_state ;
end if; N,D
end process transition; S3
open
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Copyright 2006 – Biz/ed
26. Session 6
http://www.bized.co.uk
Next State logic process
Responsible for generating the next state logic.
Reset
next_state :process(N,D,p_state)
--p_state in list to trigger process if ips are constants S0
begin
case p_state is N
when s0 => when s2 =>
if N='1' then if N='1' then S1 D
n_state <= s1; n_state <= s3;
elsif D='1' then elsif D='1' then
n_state <= s2; n_state <= s3;
N
else
n_state <= s0;
else n_state <= s2; D S2
end if;
end if;
when s1 => when s3 => N,D
if N='1' then n_state <= s0;
n_state <= s2; -------------- S3
elsif D='1' then end case;
n_state <= s3;
else n_state <= s1;
end process next_state; open
end if;
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Copyright 2006 – Biz/ed
27. Session 6
http://www.bized.co.uk
Output logic process
Responsible for generating the output logic. Reset
output_logic :process(p_state)
S0
begin
case p_state is N
when s0 => tank_open <='0'; S1
when s1 => tank_open <='0';
D
when s2 => tank_open <='0';
when s3 => tank_open <='1'; N
end case; D S2
end process output_logic ;
N,D
end Behavioral; S3
open
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Copyright 2006 – Biz/ed
28. Session 6
http://www.bized.co.uk
Step 4
Write VHDL code (Mealy)
Reset
Note : the number of states in Mealy FSM 3 !!
library IEEE; S0
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; N, 0
entity vend_machine_moore is N/D, 1 D, 1 S1 D, 0
Port (N : in STD_LOGIC;
D : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
N, 0
tank_open : out STD_LOGIC);
end vend_machine_moore; S2
architecture Behavioral of vend_machine_mealy is
type states is (s0,s1,s2);
signal n_state,p_state :states;
begin
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29. Session 6
http://www.bized.co.uk
transition :process(reset,clk)
begin
if clr='1' then
p_state <=s0 ;
elsif rising_edge(clk) then
p_state <= n_state ;
end if;
end process transition;
next_state :process(N,D,p_state)
begin
case p_state is
when s0 =>
if N='1' then
tank_open <='0';
n_state <= s1;
elsif D='1' then
n_state <= s2;
tank_open <='0';
else n_state <= s0;
tank_open <='0';
end if;
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30. Session 6
http://www.bized.co.uk
when s1 =>
if N='1' then
n_state <= s2;
tank_open <='0';
elsif D='1' then
n_state <= s0;
tank_open <='1';
else n_state <= s1;
tank_open <='0';
end if;
when s2 =>
if N='1' then
n_state <= s0;
tank_open <='1';
elsif D='1' then
n_state <= s0;
tank_open <='1';
else n_state <= s2;
tank_open <='0';
end if;
end case;
end process next_state;
end Behavioral;
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