Xilinx ise tutorial-a

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The document is a tutorial for using Xilinx ISE 10.1 software for synthesis and simulation of FPGA designs. It outlines the initial steps which include opening the software, setting preferences, creating a new project, adding VHDL files, checking syntax, and performing behavioral simulation. The tutorial explains how to view the design schematic after writing code, force inputs during simulation, and add cursors to view signal values at different times.

http://www.bized.co.uk

Xilinx ISE 10.1 tutorial A

Prepared by
Alaa Salah Shehata
Mahmoud A. M. Abd El Latif
Mohamed Mohamed Tala’t
Mohamed Salah Mahmoud

Version 02 – October 2011
Copyright 2006 – Biz/ed

http://www.bized.co.uk

Synthesis first steps

Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

First click on the ISE program to open it … 3
This screen will appear click ok or see tips of the day  Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

In first use of the program : from toolbar choose : 4
Edit menu >> preferences >>Select (integrated Tools) from the left side . 2006 – Biz/ed
Copyright

tutorial

http://www.bized.co.uk

From the first line press on the bottom beside (default) as shown 5
A new menu will appear select desktop to see( Modelsim) shortcutCopyright 2006 – Biz/ed
.

tutorial

http://www.bized.co.uk

6
A new menu will appear select desktop to see( Modelsim) shortcut .Select
Modelsim SE 6.4c (so this program you will use it as your simulation tool ) 2006 – Biz/ed
Copyright

tutorial

http://www.bized.co.uk

Now you are ready to make new project .

Note : this previous steps you will make it only one time in your first use of
the program.

7
Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

From file …. Choose ..new project
Choose your project name & project location you will save it in .
This window will appear to you : you will determine you FPGA type and its
family …and speed duo to its datasheet.
8
Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

9
Now your new project will appear in this window on its left
Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

You need to add your project files (as your project components) so
Click Right on your project file then choose (new source) then VHDL module
from your menu then determine its name .
10
Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

You can specify your block(Entity) ports from this window …. Select each port 11
type (In or out) and select each port (size) . Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

12
You are ready to write your code in this new file . Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

If there are no errors in your code
check syntax process will succeed
you can be able to make next steps
you will know it later in the tutorial

After writing your code you need first to check syntax 13
From process menu open synthesize then double click on check syntax . 2006 – Biz/ed
Copyright

tutorial

http://www.bized.co.uk

To see your block press on view RTL schematic and double click on the block to see
the Hardware that your code express . ( the tool translate your code into Hardware ).
14
Copyright 2006 – Biz/ed

http://www.bized.co.uk

Simulation first steps

Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

To perform simulation on your project : 16
From source menu select Behavioral Simulation instead of implementation .2006 – Biz/ed
Copyright

tutorial

http://www.bized.co.uk

From Modelsim Simulator double click on
Simulate Behavioral Model simulation
program(ModelSim ) will be opened .

To perform simulation on your project : 17
From source menu select Behavioral Simulation instead of implementation .2006 – Biz/ed
Copyright

tutorial

http://www.bized.co.uk

You will right click on your inputs and select Force to enter a value in this
input .
Press on run to make your required simulation .

18
Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

You can add cursor to know any signal value at any specified time in your 19
simulation . Copyright 2006 – Biz/ed

tutorial

http://www.bized.co.uk

See You Next Session

20
Copyright 2006 – Biz/ed

This document provides a tutorial on creating a simple project in Xilinx ISE 9.2. It involves starting a new project, selecting device properties, adding and writing a VHDL source file with inputs, outputs, and a counter, creating a constraint file, generating a configuration file, and uploading the configuration to an FPGA device. The overall process demonstrates how to set up a basic project from start to loading a design on an FPGA.

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Xilinx ise tutorial-a

1. http://www.bized.co.uk Xilinx ISE 10.1 tutorial A Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed

4. tutorial http://www.bized.co.uk In first use of the program : from toolbar choose : 4 Edit menu >> preferences >>Select (integrated Tools) from the left side . 2006 – Biz/ed Copyright

6. tutorial http://www.bized.co.uk 6 A new menu will appear select desktop to see( Modelsim) shortcut .Select Modelsim SE 6.4c (so this program you will use it as your simulation tool ) 2006 – Biz/ed Copyright

8. tutorial http://www.bized.co.uk From file …. Choose ..new project Choose your project name & project location you will save it in . This window will appear to you : you will determine you FPGA type and its family …and speed duo to its datasheet. 8 Copyright 2006 – Biz/ed

10. tutorial http://www.bized.co.uk You need to add your project files (as your project components) so Click Right on your project file then choose (new source) then VHDL module from your menu then determine its name . 10 Copyright 2006 – Biz/ed

13. tutorial http://www.bized.co.uk If there are no errors in your code check syntax process will succeed you can be able to make next steps you will know it later in the tutorial After writing your code you need first to check syntax 13 From process menu open synthesize then double click on check syntax . 2006 – Biz/ed Copyright

14. tutorial http://www.bized.co.uk To see your block press on view RTL schematic and double click on the block to see the Hardware that your code express . ( the tool translate your code into Hardware ). 14 Copyright 2006 – Biz/ed

16. tutorial http://www.bized.co.uk To perform simulation on your project : 16 From source menu select Behavioral Simulation instead of implementation .2006 – Biz/ed Copyright

17. tutorial http://www.bized.co.uk From Modelsim Simulator double click on Simulate Behavioral Model simulation program(ModelSim ) will be opened . To perform simulation on your project : 17 From source menu select Behavioral Simulation instead of implementation .2006 – Biz/ed Copyright

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