This document summarizes the evolution of low power DRAM designs from the 1970s to today. It discusses how DRAM power dissipation has been reduced through techniques like partial word line activation, divided bit lines, lower operating voltages, and refresh charge reduction. Future challenges include reducing subthreshold leakage as threshold voltages scale lower. The document proposes a project to design and optimize an address decoder for low power DRAM applications.

1. Low Voltage Low Power Dram
Robert Mills
Presentation for:
High Speed and Low Power VLSI design course
Instructor: Prof. M. Shams

2. Introduction
Rapidly growing area of Power Aware systems
DRAM Design Evolution
Goal: Identify Power Sources in Drams
Present Design Solutions
Examine Ultra Low Power issues (Future
Concerns)
Proposed Project Plan and Schedule

3. DRAM Evolution
Market object: Minimize cost / bit stored
1973 4Kb, NMOS, 1T1C Cell, 460mW, 300ns
1986 1Mb, CMOS, Boosted circuits, Vdd / 2 bit line
reference, 200mW, 100ns
1996 64Mb, Cell over bit line, 512 cells per column,
180mW, 60ns
2001 4Gb, Twisted Open Bit line, 270mW, trc= 70ns

4. 1T 1C Dram Cell
Word or Row Line
Data or Column line
Vdd / 2
Potential = Vcc for logic 1 and gnd
For logic 0.
Q = Vcc/2 C  logic 1
Q = -Vcc/2 C  logic 0

5. Simple Array Scheme
WL0 WL1 WL2 WL3
D0 D0*
D1 D1*

6. Trend in Power Dissipation of DRAMS
4K
16K
64K
256K
1M
64M
4M
16M 256M
200
400
600 nmos
cmos
Power
(mW)
Memory Capacity (bits)

7. RAM Chip
ARRAY
Column DE
Row
DE
Periphery
Circuits
M
N

8. Unified Power Active Equation
P = Vdd Idd
Idd = miact + m(n-1)ihold + (n+m)Cde Vint F + Cpt Vint F
+ Idcp
At high frequency ac current dominates
Idd Increases with increasing m x n array size

9. Destructive Read out
 On Readout Data line Charged and
Discharged
 Idd = (mCD DV + Cpt Vint )F
 Reduce Active Power:
1. Reduce charging cap
2. Lower Vint and Vext
3. Reduce Static current

10. Data Retention Power sources
The Refresh Operation reads data of m cells on
the nth word line
An Idd flows each time m cells are refreshed
Frequency refresh current is n / tref

11. Low Power Dram Circuits
Charge Capacitance Reduction by partial
activation of Multi-divided data line.
Increase in memory cells directly increases the
CD
Divide one data line into several sections &
activate only one sub-section.

12. Multi-divided data-line & Word Line
Y SA
X Decoder
A2 SA
A3 A4
Y A5 SA A6 SA
A7
Shared Y-decoder, X-decoder and Sense Amp

13. Reduction in CDT & QDT
Employing Partial Activation +
Multi divided data line and Word lines
For 256Mb DRAM design Cdt expected drop from
3000 pf to 100pf.
Charge Reduction on Qdt from 3100 pC to
102 pC for experimental 256 Mb DRAM

14. Operating Voltage Reduction
Reduction in Vdd helps reduces Decoder and
Perpheral logic power.
CMOS vs nMOS decoders
Half Vdd data-line pre charge lower power in
memory array
CMOS circuit - P = 0.46 : A = 0.7
NMOS circuit - P = 1 : A = 1

15. Half Vdd Pre - charging Scheme
fp
Vdd/2
fr
0
D
D
fa fr fp
fa

16. DC Current Reduction
Column signal path circuitry main source of static
current.
DC current flows from the I/O line load to the data
lines while column is switched on.
Use Address Transition Detection (ATD) circuitry
to activate column switch and main amplifier.

17. Data Reduction Power Retention
Use Voltage conversion circuits
Use Refresh Time extension
Refresh Charge Reduction

18. Low Power circuit Advancement
64Mb DRAM (110ns cycle)
1980
25.4 W
DE 500 Periphery 640 Array 24.2W
1994
47mW
Low V 3.3 -> 1.5v
Low C ( part. Act. M-D WL)
1990
304mW
48 168 88
Low Idc ( CMOS Cir, ATD)
Low C ( CMOS NAND Dec,
Part. Act. M-D Data.Line.)
Low V 5 -> 3.3v

19. Ultra Low Power Concerns
Vt Scaling is major concern for achieving ultra-
low voltage power VLSI’s.
DC chip current due to sub threshold current Idc
increases exponentially with Vt reduction when
Vdd is lowered.
This problem affects data retention current as
well as active current.

20. Trends in Active Current for DRAMS
Capacity 256M 1G 4G 16G 64G
10e-1
10e-3
10e-2
10
1
Current
(A)
Iac
Iact
Idc
Vdd
Vt
2v 1.5v 1.2v 1v 0.8v
0.32v 0.24v 0.19v 0.16v 0.13v

21. Retention Problem
In a Cell, sub-threshold leakage current flow from
the capacitor to the data line.
This degrades the data retention time
Drams cells require highest Vt
WL
DL
Cs
1
0

22. Two Reduction schemes
The dynamic Vt scheme
In active mode Vt is set low. In stand-by mode
the Vt is raised
The Static Vt scheme
Categorized as power-switch and multi Vt
scheme.

23. Conclusion
Source for power dissipation in Drams have been
examined
Architectures and Circuits have been reviewed to
address these power hungry area.
Future Dram designer need to address
Increasing sub-threshold current as Idc >> Iac.

24. Project Plan & Schedule
 Design an Address Decoder and Optimize for low power DRAM
application.
 Define design problem: 1st – 7th April
 Optimize & design Decoder: 8 -15th April
 Simulate both designs: 16-22th April
 Present Results week of 23rd April
 Submit in report on 5th May

25. References
 “Fast Low Power Decoders for Rams”, M. Horowitz, IEEE JSSC, Vol,36, No.10,
Oct 2001
 “Low Voltage Memories for Power-Aware Systems”,Itoh, ISLPED ’02, August
12-14, 2002, Monterey, California, USA.
 “A 4Gb DDR SDRAM with Gain controlled Pre-Sensing and Ref. Bitline
Calibration Schemes in the twisted Open Bitline Architecture”, H. Yoon et al.,
IEEE, ISSCC-2001 Session 24/DRAM/24.1, Feb. 2001
 “Limitations and Challenges of Multigigabit DRAM Chip Design”, Itoh, IEEE
JSSC, Vol. 32, No. 5, May 1997.
 “Trends in Low Power RAM Circuit Technologies”, Itoh et al, Proceedings of the
IEEE, Vol. 83, No.4 April 1995.