SlideShare a Scribd company logo
1 of 9
RELATION BETWEEN
DATA WORD SIZE
AND
INSTRUCTION WORD SIZE
DIGITAL SIGNAL PROCESSOR
AND ARCHITECTURE
NITHIN KALLEPALLY
• In computing, a word is the natural unit of data used by a particular processor design.
A word is a fixed-sized piece of data handled as a unit by the instruction set or the
hardware of the processor.The number of bits in a word (the word size, word width,
or word length) is an important characteristic of any specific processor design
or computer architecture.
• The size of a word is reflected in many aspects of a computer's structure and operation;
the majority of the registers in a processor are usually word sized and the largest piece of
data that can be transferred to and from the working memory in a single operation is a
word in many (not all) architectures.The largest possible address size, used to designate
a location in memory, is typically a hardware word (here, "hardware word" means the
full-sized natural word of the processor, as opposed to any other definition used).
• WORD SIZE
• All common floating-point DSPs use a 32-bit data word. For fixed-point
DSPs, the most common data word size is 16 bits. Motorola’s DSP563xx
family uses a 24-bit data word, however, while Zoran’s ZR3800x family uses
a 20-bit data word.The size of the data word has a major impact on cost,
because it strongly influences the size of the chip and the number of
package pins required, as well as the size of external memory devices
connected to the DSP.Therefore, designers try to use the chip with the
smallest word size that their application can tolerate.
• As with the choice between fixed and floating point chips, there is often a
trade-off between word size and development complexity.
• For example, with a 16-bit fixed-point processor, a programmer can
perform double-precision 32-bit arithmetic operations by stringing together
an appropriate combination of instructions. (Of course, double-precision
arithmetic is much slower than single-precision arithmetic.) If the bulk of an
application can be handled with single-precision arithmetic, but the
application needs more precision for a small section of the code, the
selective use of double-precision arithmetic may make sense. If most of the
application requires more precision, a processor with a larger data word size
is likely to be a better choice.
• Note that while most DSP processors use an instruction word size
equal to their data word size, not all does.The Analog Devices ADSP-
21xx family, for example, uses a 16-bit data word and a 24-bit
instruction word.
•An instruction is assembled in binary form(0,1) known as
machine code or opcode. Due to different ways of specifying
data or operand the machine code are not same for all the
instruction .The size of an instruction signifies how much
memory space is required to load an instruction in the
memory.
INSTRUCTION WORD
• 1. One-byte instructions –
In 1-byte instruction, the opcode and the operand of an instruction are represented in one byte.
• Note –The length of these instructions is 8-bit; each requires one memory location.
• 2.Two-byte instructions –
Two-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and the next 8
bits indicates the operand.
• Note –This type of instructions need two bytes to store the binary codes.
• 3.Three-byte instructions –
Three-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and the next
two bytes specify the 16-bit address.The low-order address is represented in second byte and the high-
order address is represented in the third byte.
• Note –These instructions would require three memory locations to store the binary codes
Precision (Fixed-Point Binary Representation)
Dynamic Range (# of bits per data word x 6 db/bit or resolution)
16-bit 96 dB
24-bit 144 dB
32-bit 192 dB
When a computer architecture is designed, the choice of a word size is of substantial importance.There are
design considerations which encourage particular bit-group sizes for particular uses (e.g. for addresses), and
these considerations point to different sizes for different uses. However, considerations of economy in
design strongly push for one size, or a very few sizes related by multiples or fractions (submultiples) to a
primary size.That preferred size becomes the word size of the architecture.
THANK YOU…

More Related Content

Similar to RELATION BETWEEN DATA WORD SIZE AND INSTRUCTION WORD SIZE- Dspa word size

64 bit computing
64 bit computing64 bit computing
64 bit computing
Ankita Nema
 

Similar to RELATION BETWEEN DATA WORD SIZE AND INSTRUCTION WORD SIZE- Dspa word size (20)

Operating system
Operating systemOperating system
Operating system
 
Microprocessor
MicroprocessorMicroprocessor
Microprocessor
 
SS-CISC -1.pptx
SS-CISC -1.pptxSS-CISC -1.pptx
SS-CISC -1.pptx
 
Os4
Os4Os4
Os4
 
Os4
Os4Os4
Os4
 
Memory management in sql server
Memory management in sql serverMemory management in sql server
Memory management in sql server
 
Module-2 Instruction Set Cpus.pdf
Module-2 Instruction Set Cpus.pdfModule-2 Instruction Set Cpus.pdf
Module-2 Instruction Set Cpus.pdf
 
Architectural support for High Level Language
Architectural support for High Level LanguageArchitectural support for High Level Language
Architectural support for High Level Language
 
Cache memory
Cache memoryCache memory
Cache memory
 
Memory management
Memory managementMemory management
Memory management
 
M&i(lec#01)
M&i(lec#01)M&i(lec#01)
M&i(lec#01)
 
Computer architecture instruction formats
Computer architecture instruction formatsComputer architecture instruction formats
Computer architecture instruction formats
 
Fundamentals.pptx
Fundamentals.pptxFundamentals.pptx
Fundamentals.pptx
 
Protected addressing mode and Paging
Protected addressing mode and PagingProtected addressing mode and Paging
Protected addressing mode and Paging
 
64 bit computing
64 bit computing64 bit computing
64 bit computing
 
EE5440 – Computer Architecture - Lecture 2
EE5440 – Computer Architecture - Lecture 2EE5440 – Computer Architecture - Lecture 2
EE5440 – Computer Architecture - Lecture 2
 
Arm cortex-m4 programmer model
Arm cortex-m4 programmer modelArm cortex-m4 programmer model
Arm cortex-m4 programmer model
 
Memory Management Strategies - III.pdf
Memory Management Strategies - III.pdfMemory Management Strategies - III.pdf
Memory Management Strategies - III.pdf
 
Bab 4
Bab 4Bab 4
Bab 4
 
Memory Addressing
Memory AddressingMemory Addressing
Memory Addressing
 

More from NITHIN KALLE PALLY

ANALYTIC SIGNAL GENERATION- DIGITAL SIGNAL PROCESSORS AND ARCHITECTURE ...
ANALYTIC SIGNAL GENERATION- DIGITAL SIGNAL PROCESSORS AND ARCHITECTURE       ...ANALYTIC SIGNAL GENERATION- DIGITAL SIGNAL PROCESSORS AND ARCHITECTURE       ...
ANALYTIC SIGNAL GENERATION- DIGITAL SIGNAL PROCESSORS AND ARCHITECTURE ...
NITHIN KALLE PALLY
 

More from NITHIN KALLE PALLY (15)

Formats for coherent optical communications -OPTICAL COMMUNICATIONS
Formats for coherent optical communications -OPTICAL COMMUNICATIONSFormats for coherent optical communications -OPTICAL COMMUNICATIONS
Formats for coherent optical communications -OPTICAL COMMUNICATIONS
 
Based Interferometric Sensors- OPTICAL COMMUNICATION
Based Interferometric Sensors- OPTICAL COMMUNICATIONBased Interferometric Sensors- OPTICAL COMMUNICATION
Based Interferometric Sensors- OPTICAL COMMUNICATION
 
SHORT CHANNEL EFFECTS IN MOSFETS- VLSI DESIGN
SHORT CHANNEL EFFECTS IN MOSFETS- VLSI DESIGNSHORT CHANNEL EFFECTS IN MOSFETS- VLSI DESIGN
SHORT CHANNEL EFFECTS IN MOSFETS- VLSI DESIGN
 
ANALYTIC SIGNAL GENERATION- DIGITAL SIGNAL PROCESSORS AND ARCHITECTURE ...
ANALYTIC SIGNAL GENERATION- DIGITAL SIGNAL PROCESSORS AND ARCHITECTURE       ...ANALYTIC SIGNAL GENERATION- DIGITAL SIGNAL PROCESSORS AND ARCHITECTURE       ...
ANALYTIC SIGNAL GENERATION- DIGITAL SIGNAL PROCESSORS AND ARCHITECTURE ...
 
VLAN -VIRTUAL LAN -COMPUTER NETWORKS
VLAN -VIRTUAL LAN -COMPUTER NETWORKSVLAN -VIRTUAL LAN -COMPUTER NETWORKS
VLAN -VIRTUAL LAN -COMPUTER NETWORKS
 
CMOS Fabrication using P-well -VLSI
CMOS Fabrication  using P-well -VLSICMOS Fabrication  using P-well -VLSI
CMOS Fabrication using P-well -VLSI
 
Gray Image Watermarking using slant transform - digital image processing
Gray Image Watermarking using slant transform - digital image processingGray Image Watermarking using slant transform - digital image processing
Gray Image Watermarking using slant transform - digital image processing
 
web2.0 - computer networks
web2.0 - computer networksweb2.0 - computer networks
web2.0 - computer networks
 
DISTINGUISH BETWEEN WALSH TRANSFORM AND HAAR TRANSFORMDip transforms
DISTINGUISH BETWEEN WALSH TRANSFORM AND HAAR TRANSFORMDip transformsDISTINGUISH BETWEEN WALSH TRANSFORM AND HAAR TRANSFORMDip transforms
DISTINGUISH BETWEEN WALSH TRANSFORM AND HAAR TRANSFORMDip transforms
 
Need of research and types of research
Need of research and types of researchNeed of research and types of research
Need of research and types of research
 
8051 architecture and pin configuration
8051 architecture and pin configuration8051 architecture and pin configuration
8051 architecture and pin configuration
 
TRANSITIONAL BUTTERWORTH-CHEBYSHEV FILTERS
TRANSITIONALBUTTERWORTH-CHEBYSHEV FILTERSTRANSITIONALBUTTERWORTH-CHEBYSHEV FILTERS
TRANSITIONAL BUTTERWORTH-CHEBYSHEV FILTERS
 
CAUSES AND EFFECTS OF LANDSLIDES
CAUSES AND EFFECTS OF LANDSLIDESCAUSES AND EFFECTS OF LANDSLIDES
CAUSES AND EFFECTS OF LANDSLIDES
 
FUTURE PUBLIC LAND MOBILE TELECOMMUNICATION SYSTEMS(FPLMTS) AND INFORMA...
      FUTURE PUBLIC LAND MOBILE TELECOMMUNICATION SYSTEMS(FPLMTS) AND INFORMA...      FUTURE PUBLIC LAND MOBILE TELECOMMUNICATION SYSTEMS(FPLMTS) AND INFORMA...
FUTURE PUBLIC LAND MOBILE TELECOMMUNICATION SYSTEMS(FPLMTS) AND INFORMA...
 
SAMPLING AND STORAGE OSCILLOSCOPE
SAMPLING AND STORAGE OSCILLOSCOPESAMPLING AND STORAGE OSCILLOSCOPE
SAMPLING AND STORAGE OSCILLOSCOPE
 

Recently uploaded

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
ssuser89054b
 
"Lesotho Leaps Forward: A Chronicle of Transformative Developments"
"Lesotho Leaps Forward: A Chronicle of Transformative Developments""Lesotho Leaps Forward: A Chronicle of Transformative Developments"
"Lesotho Leaps Forward: A Chronicle of Transformative Developments"
mphochane1998
 
notes on Evolution Of Analytic Scalability.ppt
notes on Evolution Of Analytic Scalability.pptnotes on Evolution Of Analytic Scalability.ppt
notes on Evolution Of Analytic Scalability.ppt
MsecMca
 
Standard vs Custom Battery Packs - Decoding the Power Play
Standard vs Custom Battery Packs - Decoding the Power PlayStandard vs Custom Battery Packs - Decoding the Power Play
Standard vs Custom Battery Packs - Decoding the Power Play
Epec Engineered Technologies
 
+97470301568>> buy weed in qatar,buy thc oil qatar,buy weed and vape oil in d...
+97470301568>> buy weed in qatar,buy thc oil qatar,buy weed and vape oil in d...+97470301568>> buy weed in qatar,buy thc oil qatar,buy weed and vape oil in d...
+97470301568>> buy weed in qatar,buy thc oil qatar,buy weed and vape oil in d...
Health
 

Recently uploaded (20)

Learn the concepts of Thermodynamics on Magic Marks
Learn the concepts of Thermodynamics on Magic MarksLearn the concepts of Thermodynamics on Magic Marks
Learn the concepts of Thermodynamics on Magic Marks
 
Rums floating Omkareshwar FSPV IM_16112021.pdf
Rums floating Omkareshwar FSPV IM_16112021.pdfRums floating Omkareshwar FSPV IM_16112021.pdf
Rums floating Omkareshwar FSPV IM_16112021.pdf
 
HAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKAR
HAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKARHAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKAR
HAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKAR
 
FEA Based Level 3 Assessment of Deformed Tanks with Fluid Induced Loads
FEA Based Level 3 Assessment of Deformed Tanks with Fluid Induced LoadsFEA Based Level 3 Assessment of Deformed Tanks with Fluid Induced Loads
FEA Based Level 3 Assessment of Deformed Tanks with Fluid Induced Loads
 
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 
"Lesotho Leaps Forward: A Chronicle of Transformative Developments"
"Lesotho Leaps Forward: A Chronicle of Transformative Developments""Lesotho Leaps Forward: A Chronicle of Transformative Developments"
"Lesotho Leaps Forward: A Chronicle of Transformative Developments"
 
S1S2 B.Arch MGU - HOA1&2 Module 3 -Temple Architecture of Kerala.pptx
S1S2 B.Arch MGU - HOA1&2 Module 3 -Temple Architecture of Kerala.pptxS1S2 B.Arch MGU - HOA1&2 Module 3 -Temple Architecture of Kerala.pptx
S1S2 B.Arch MGU - HOA1&2 Module 3 -Temple Architecture of Kerala.pptx
 
Air Compressor reciprocating single stage
Air Compressor reciprocating single stageAir Compressor reciprocating single stage
Air Compressor reciprocating single stage
 
Computer Networks Basics of Network Devices
Computer Networks  Basics of Network DevicesComputer Networks  Basics of Network Devices
Computer Networks Basics of Network Devices
 
notes on Evolution Of Analytic Scalability.ppt
notes on Evolution Of Analytic Scalability.pptnotes on Evolution Of Analytic Scalability.ppt
notes on Evolution Of Analytic Scalability.ppt
 
A CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptx
A CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptxA CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptx
A CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptx
 
School management system project Report.pdf
School management system project Report.pdfSchool management system project Report.pdf
School management system project Report.pdf
 
data_management_and _data_science_cheat_sheet.pdf
data_management_and _data_science_cheat_sheet.pdfdata_management_and _data_science_cheat_sheet.pdf
data_management_and _data_science_cheat_sheet.pdf
 
Thermal Engineering -unit - III & IV.ppt
Thermal Engineering -unit - III & IV.pptThermal Engineering -unit - III & IV.ppt
Thermal Engineering -unit - III & IV.ppt
 
Navigating Complexity: The Role of Trusted Partners and VIAS3D in Dassault Sy...
Navigating Complexity: The Role of Trusted Partners and VIAS3D in Dassault Sy...Navigating Complexity: The Role of Trusted Partners and VIAS3D in Dassault Sy...
Navigating Complexity: The Role of Trusted Partners and VIAS3D in Dassault Sy...
 
Unleashing the Power of the SORA AI lastest leap
Unleashing the Power of the SORA AI lastest leapUnleashing the Power of the SORA AI lastest leap
Unleashing the Power of the SORA AI lastest leap
 
Standard vs Custom Battery Packs - Decoding the Power Play
Standard vs Custom Battery Packs - Decoding the Power PlayStandard vs Custom Battery Packs - Decoding the Power Play
Standard vs Custom Battery Packs - Decoding the Power Play
 
2016EF22_0 solar project report rooftop projects
2016EF22_0 solar project report rooftop projects2016EF22_0 solar project report rooftop projects
2016EF22_0 solar project report rooftop projects
 
+97470301568>> buy weed in qatar,buy thc oil qatar,buy weed and vape oil in d...
+97470301568>> buy weed in qatar,buy thc oil qatar,buy weed and vape oil in d...+97470301568>> buy weed in qatar,buy thc oil qatar,buy weed and vape oil in d...
+97470301568>> buy weed in qatar,buy thc oil qatar,buy weed and vape oil in d...
 
Computer Lecture 01.pptxIntroduction to Computers
Computer Lecture 01.pptxIntroduction to ComputersComputer Lecture 01.pptxIntroduction to Computers
Computer Lecture 01.pptxIntroduction to Computers
 

RELATION BETWEEN DATA WORD SIZE AND INSTRUCTION WORD SIZE- Dspa word size

  • 1. RELATION BETWEEN DATA WORD SIZE AND INSTRUCTION WORD SIZE DIGITAL SIGNAL PROCESSOR AND ARCHITECTURE NITHIN KALLEPALLY
  • 2. • In computing, a word is the natural unit of data used by a particular processor design. A word is a fixed-sized piece of data handled as a unit by the instruction set or the hardware of the processor.The number of bits in a word (the word size, word width, or word length) is an important characteristic of any specific processor design or computer architecture. • The size of a word is reflected in many aspects of a computer's structure and operation; the majority of the registers in a processor are usually word sized and the largest piece of data that can be transferred to and from the working memory in a single operation is a word in many (not all) architectures.The largest possible address size, used to designate a location in memory, is typically a hardware word (here, "hardware word" means the full-sized natural word of the processor, as opposed to any other definition used).
  • 3. • WORD SIZE • All common floating-point DSPs use a 32-bit data word. For fixed-point DSPs, the most common data word size is 16 bits. Motorola’s DSP563xx family uses a 24-bit data word, however, while Zoran’s ZR3800x family uses a 20-bit data word.The size of the data word has a major impact on cost, because it strongly influences the size of the chip and the number of package pins required, as well as the size of external memory devices connected to the DSP.Therefore, designers try to use the chip with the smallest word size that their application can tolerate. • As with the choice between fixed and floating point chips, there is often a trade-off between word size and development complexity.
  • 4. • For example, with a 16-bit fixed-point processor, a programmer can perform double-precision 32-bit arithmetic operations by stringing together an appropriate combination of instructions. (Of course, double-precision arithmetic is much slower than single-precision arithmetic.) If the bulk of an application can be handled with single-precision arithmetic, but the application needs more precision for a small section of the code, the selective use of double-precision arithmetic may make sense. If most of the application requires more precision, a processor with a larger data word size is likely to be a better choice.
  • 5. • Note that while most DSP processors use an instruction word size equal to their data word size, not all does.The Analog Devices ADSP- 21xx family, for example, uses a 16-bit data word and a 24-bit instruction word.
  • 6. •An instruction is assembled in binary form(0,1) known as machine code or opcode. Due to different ways of specifying data or operand the machine code are not same for all the instruction .The size of an instruction signifies how much memory space is required to load an instruction in the memory. INSTRUCTION WORD
  • 7. • 1. One-byte instructions – In 1-byte instruction, the opcode and the operand of an instruction are represented in one byte. • Note –The length of these instructions is 8-bit; each requires one memory location. • 2.Two-byte instructions – Two-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and the next 8 bits indicates the operand. • Note –This type of instructions need two bytes to store the binary codes. • 3.Three-byte instructions – Three-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and the next two bytes specify the 16-bit address.The low-order address is represented in second byte and the high- order address is represented in the third byte. • Note –These instructions would require three memory locations to store the binary codes
  • 8. Precision (Fixed-Point Binary Representation) Dynamic Range (# of bits per data word x 6 db/bit or resolution) 16-bit 96 dB 24-bit 144 dB 32-bit 192 dB When a computer architecture is designed, the choice of a word size is of substantial importance.There are design considerations which encourage particular bit-group sizes for particular uses (e.g. for addresses), and these considerations point to different sizes for different uses. However, considerations of economy in design strongly push for one size, or a very few sizes related by multiples or fractions (submultiples) to a primary size.That preferred size becomes the word size of the architecture.