resume, Brian Hiltscher

1. Brian Hiltscher
Technical Lead, Software Engineer
brianhiltscher@gmail.com
(919) 368-1753
Software engineer with extensive experience in real-time, networking software development.
Motivated, solutions oriented team player with excellent communication and problem solving
skills. Possess a Bachelor of Science degree in Computer Science from Brigham Young
University.
Skills
“C”, Linux, networking, multithreaded programming, embedded software, classification
algorithms, performance tuning, simulation, real-time OS, IXIA, Spirent, GIT, X Windows, QOS,
Perl, Python, X86 assembly, tensilica assembly, various other assembly languages. Intel X86,
PowerPC, Motorola 680x0.
Experience
Cisco Systems, February 2000 – present
• February 2019-present. Design, implement and test various performance enhancements
for a new software based Cisco ASR1000 product, including the following:
o Integrate the Intel transactional memory capability into the dataplane
infrastructure logic in order to guarantee atomicity without locking.
o 64-bit dataplane conversion study. Identify changes required, as well as level of
effort to convert the 32-bit software dataplane to support 64-bit addressing.
o Implement and test a credit sharing scheme between the receive (RX) process,
and the Packet Processors (PPEs), in order to avoid oversubscription of the PPEs.
• 2017-2019. Integration of a new network processor ASIC for the Cisco ASR1000 router.
Responsibilities included the following:
o Adaptation of the EtherChannel dataplane to support network processor
hardware assist logic.
o Crypto software performance tuning.
o Buffering, queueing, and scheduling (BQS) hardware assist software adaptation,
including conditional policing, re-enqueue, rate profiles, and out of resource
(OOR) logic.
o Implementation and performance tuning of descriptor transfer logic (DTL)
emulation software.
• 2014-2017. Next generation performance improvement project for Cisco Cloud Services
Router (CSR). Responsibilities included the following:
o Prototyping, selection of packet scheduler, and queuing engine.
o Design, and implementation of a multi-threaded version of our hierarchical
scheduler (HQF).
o Prototyping, design, and implementation of flow-based distribution (FBD).

2. o Flow based QOS statistics. Design and implement the dataplane, and control
plane logic for the atomic, but non-locking QOS statistics.
• 2014. IPV4 forwarding software conversion for Cisco Cloud Services Router (CSR).
Designed and implemented the IPV4 forwarding software changes from the Tree bitmap
(TBM) algorithm to MTRIE. These changes were made in order to realize a major
performance improvement over TBM.
• 2012-2014. Software based classification. Design, and implement the classification
engine for new software-based platforms (CSR, and ISR), that do not have TCAM based,
or any other hardware acceleration.
• 2008-2011. ASR1000 Buffering, Queueing, and scheduling (BQS). Implement control
plane software for the BQS ASIC. Responsibilities included the following:
o Packet rate profile programming and selection.
o Conditional policing, congestion detection, and out of resource (OOR) dataplane
and control plane logic.
o Priority propagation.
• 2005-2006. ASR1000 QOS feature design and implementation. Responsibilities
included:
o Packet marking.
o Rate limiting (policing).
o Packet classification.
o Drop policy, including weighted random early detection (WRED), fair-queue, and
tail-drop.
o Statistics collection, and checksum calculation.
o Packet simulation.
• 2006-2007. Common Classification Engine (CCE) design and implementation. Design
and implement a generic method of performing packet classification using a TCAM for
hardware acceleration. Responsibilities included:
o Definition of feature specific TCAM keys.
o Method to convey opaque feature specific data post-classification.
o Dataplane logic for both 160b and 320b TCAM searches.
o Associated simulation support.
• 2001-2004. Hierarchical Scheduler, on Cisco 7600 series router. Designed, and
implemented a multi-threaded, queueing engine, and hierarchical scheduler targeted
for the Castine Network processor.
• 2001. DOCSIS QOS dataplane for Cisco UBR10000. Designed and implemented the
Cable/DOCSIS QOS dataplane for the first-generation Cisco network processor.
• 2000. QOS dataplane for Cisco C10000. Designed and implemented the QOS dataplane
for the first-generation Cisco network processor.
Nortel Networks, Research Triangle Park, NC, July 1997 – Feb. 2000
• Designed, and implemented software to support porting a telephone switch to a real-
time operating system. C & PowerPC assembly.

3. Hughes Aircraft Company, Fullerton, CA June 1983- July 1997
• TPQ36/37 radar communication encryption software, Sperry/Univac assembly.
• RSRP, air defense radar software, VAXELN pascal.
• Naval, ship board, defense system software, NTDS, assembly.
• X windows graphics software for Naval and coast guard displays, Ada, and X windows.
Motorola 68020,68030, 68040. VxWorks/VME.
Accomplishments
• Patent #US7564790: “Method and system for shaping traffic in a parallel queuing
hierarchy”. Date issued: July 21, 2009
• Patent # US8520672: “Packet switching device using results determined by an
application node”. Date issued: August 27, 2013