Presented by Mohamed Boussaa on September 6, 2017 at INRIA Rennes, France.
The dissertation is available at this link: https://hal.inria.fr/tel-01598821/document
The jury is composed of:
Hélène WAESELYNCK, LAAS-CNRS Toulouse
Philippe MERLE, INRIA Lille
Erven ROHOU, INRIA Rennes
Franck FLEUREY, SINTEF Oslo
Jean-Marie MOTTU, Université de Nantes
Gerson SUNYÉ, Université de Nantes
Benoit BAUDRY, INRIA Rennes
Olivier BARAIS, Université de Rennes 1
The aim of this research paper is to design a new pseudorandom number generator based on FCSR registers, with not affecting the speed of generation.In the main part, a deep description of the cascades used in the design and describe the working principle of GPRN. The analyzed statistical characteristics are obtained from various generated sequences using test package NIST 800-22 and then confirmed by experiment, that a modeled GPRN has a higher period of repetition and works faster.
MEME – An Integrated Tool For Advanced Computational ExperimentsGIScRG
The document describes MEME, an integrated tool for advanced computational experiments. MEME allows users to efficiently explore model responses through parameter sweeps and design of experiments. It supports running simulations in parallel on local clusters and grids. MEME collects, analyzes, and visualizes results. It implements intelligent "IntelliSweep" methods like iterative uniform interpolation and genetic algorithms to refine parameter space exploration.
II-SDV 2017: Towards Semantic Search at the European Patent OfficeDr. Haxel Consult
With the ever-increasing volume of data to be searched, the techniques of semantic search will be key to successful prior art searching. These techniques consist of methods for understanding the searcher`s intent, disambiguating the contextual meaning of (search) terms and ultimately improving search accuracy by generating more relevant results. This
presentation explores how far the EPO has come in enabling some of those key elements through projects such as Annotated Patent Literature and Enhanced Ranking. It also introduces even more sophisticated models based on machined-learned algorithms that might help to shape the future of search at the EPO.
SensLAB is a very large scale open wireless sensor network testbed consisting of over 1000 sensor nodes distributed across 4 sites in France. It aims to provide researchers with an experimental platform for developing and validating new sensor network protocols and applications through large-scale deployment and experimentation. The testbed supports heterogeneous sensor nodes and radio technologies and provides tools for remote and automated experimentation, as well as non-intrusive monitoring of experiments.
p4pktgen: Automated Test Case Generation for P4 ProgramsAJAY KHARAT
Traditional network devices - fixed set of capabilities
Rise of programmable network devices in recent years
Offers great flexibility / capability than traditional network devices
Flexibility introduces new bugs:
Hardware
Toolchains
Programs
These bugs were previously covered by traditional network devices due to fixed set of capabilities
Use test cases to check whether program is behaving as intended on the device
Enabling Large Scale Sequencing Studies through Science as a ServiceJustin Johnson
Now
“Now” generation sequencing has drastically changed the traditional costs and infrastructure within the sequencing community. There are several technologies, platforms and algorithms that show promise, but it is not always intuitive where to start. This uncertainty is compounded by the fact that commonly used analysis tools are difficult to build, maintain, and run effectively. Sample acquisition and preparation is quickly becoming a bottleneck as projects move from small sample sizes to hundreds or even thousands of samples. We will present case studies highlighting information, methods, challenges and opportunities in leveraging large scale high throughput sequencing and bioinformatics. Specifically we will highlight a recent genome-wide study of methylation patterns in 1575 individuals with Schizophrenia. We will also discuss several cancer transcriptome and exome sequencing projects as well as a human pathogen transcriptome characterization project consisting of multiple organisms and almost a billion reads.
The Future
The Ion Torrent PGM machine is a very promising, rapid throughput, ultra scalable sequencer that could play an integral part in future human health studies. Applications such as microbial whole genome sequencing, metagenomic characterization of environmental and microbiome sample, and targeted resequencing projects stand to benefit from this technology over time. To date we have completed more than 25 runs on a single PGM and will comment on the setup as well as sequence data and analysis.
The aim of this research paper is to design a new pseudorandom number generator based on FCSR registers, with not affecting the speed of generation.In the main part, a deep description of the cascades used in the design and describe the working principle of GPRN. The analyzed statistical characteristics are obtained from various generated sequences using test package NIST 800-22 and then confirmed by experiment, that a modeled GPRN has a higher period of repetition and works faster.
MEME – An Integrated Tool For Advanced Computational ExperimentsGIScRG
The document describes MEME, an integrated tool for advanced computational experiments. MEME allows users to efficiently explore model responses through parameter sweeps and design of experiments. It supports running simulations in parallel on local clusters and grids. MEME collects, analyzes, and visualizes results. It implements intelligent "IntelliSweep" methods like iterative uniform interpolation and genetic algorithms to refine parameter space exploration.
II-SDV 2017: Towards Semantic Search at the European Patent OfficeDr. Haxel Consult
With the ever-increasing volume of data to be searched, the techniques of semantic search will be key to successful prior art searching. These techniques consist of methods for understanding the searcher`s intent, disambiguating the contextual meaning of (search) terms and ultimately improving search accuracy by generating more relevant results. This
presentation explores how far the EPO has come in enabling some of those key elements through projects such as Annotated Patent Literature and Enhanced Ranking. It also introduces even more sophisticated models based on machined-learned algorithms that might help to shape the future of search at the EPO.
SensLAB is a very large scale open wireless sensor network testbed consisting of over 1000 sensor nodes distributed across 4 sites in France. It aims to provide researchers with an experimental platform for developing and validating new sensor network protocols and applications through large-scale deployment and experimentation. The testbed supports heterogeneous sensor nodes and radio technologies and provides tools for remote and automated experimentation, as well as non-intrusive monitoring of experiments.
p4pktgen: Automated Test Case Generation for P4 ProgramsAJAY KHARAT
Traditional network devices - fixed set of capabilities
Rise of programmable network devices in recent years
Offers great flexibility / capability than traditional network devices
Flexibility introduces new bugs:
Hardware
Toolchains
Programs
These bugs were previously covered by traditional network devices due to fixed set of capabilities
Use test cases to check whether program is behaving as intended on the device
Enabling Large Scale Sequencing Studies through Science as a ServiceJustin Johnson
Now
“Now” generation sequencing has drastically changed the traditional costs and infrastructure within the sequencing community. There are several technologies, platforms and algorithms that show promise, but it is not always intuitive where to start. This uncertainty is compounded by the fact that commonly used analysis tools are difficult to build, maintain, and run effectively. Sample acquisition and preparation is quickly becoming a bottleneck as projects move from small sample sizes to hundreds or even thousands of samples. We will present case studies highlighting information, methods, challenges and opportunities in leveraging large scale high throughput sequencing and bioinformatics. Specifically we will highlight a recent genome-wide study of methylation patterns in 1575 individuals with Schizophrenia. We will also discuss several cancer transcriptome and exome sequencing projects as well as a human pathogen transcriptome characterization project consisting of multiple organisms and almost a billion reads.
The Future
The Ion Torrent PGM machine is a very promising, rapid throughput, ultra scalable sequencer that could play an integral part in future human health studies. Applications such as microbial whole genome sequencing, metagenomic characterization of environmental and microbiome sample, and targeted resequencing projects stand to benefit from this technology over time. To date we have completed more than 25 runs on a single PGM and will comment on the setup as well as sequence data and analysis.
To Get any Project for CSE, IT ECE, EEE Contact Me @ 09666155510, 09849539085 or mail us - ieeefinalsemprojects@gmail.com-Visit Our Website: www.finalyearprojects.org
To Get any Project for CSE, IT ECE, EEE Contact Me @ 09666155510, 09849539085 or mail us - ieeefinalsemprojects@gmail.com-Visit Our Website: www.finalyearprojects.org
Prateep Kumar Sengupta is seeking a position as an engineer where he can contribute his skills in data science, machine learning, and R&D. He has a M.Tech in Communication Engineering and B.Tech in Electronics and Instrumentation Engineering. His skills include Python, UNIX shell scripts, Perl, and tools for data science, machine learning, web scraping, and email marketing. He has work experience in technology roles and has conducted research and published papers in machine learning and antenna optimization.
User-Assisted Log Analysis for Quality Control of Distributed Fintech Applica...Iosif Itkin
The First IEEE International Conference On Artificial Intelligence Testing (2019 IEEE AITest)
Iosif Itkin, Anna Gromova, Anton Sitnikov, Elena Treshcheva, Rostislav Yavorskiy, Evgenii Tsymbalov, Andrey Novikov and Kirill Rudakov
1 Exactpro, UK, Georgia, USA, Russia
2 Skolkovo Institute of Science and Technology, Russia
3 Higher School of Economics, Russia
Testing embedded system through optimal mining technique (OMT) based on multi...IJECEIAES
Testing embedded systems must be done carefully particularly in the significant regions of the embedded systems. Inputs from an embedded system can happen in multiple order and many relationships can exist among the input sequences. Consideration of the sequences and the relationships among the sequences is one of the most important considerations that must be tested to find the expected behavior of the embedded systems. On the other hand combinatorial approaches help determining fewer test cases that are quite enough to test the embedded systems exhaustively. In this paper, an Optimal Mining Technique that considers multi-input domain which is based on built-in combinatorial approaches has been presented. The method exploits multi-input sequences and the relationships that exist among multi-input vectors. The technique has been used for testing an embedded system that monitors and controls the temperature within the Nuclear reactors.
Ming Liu has over 10 years of experience in embedded software development and testing using languages like C/C++, Python, and Shell scripts. He has worked as a Validation Engineer at Marvell Semiconductor testing WiFi chip features and bringing up new products. Prior to that, he was a Verification Engineer at Wind River testing their VxWorks operating system and a Software Designer at Nortel Networks developing features for their UMTS wireless system.
The document summarizes the activities of PERC, including their use of tools like PAPI, SvPablo, and ROSE for performance analysis and modeling. They evaluate applications like PETSc and 8 codes from basic sciences. Several performance modeling and analysis projects are listed as ongoing, including techniques for machine learning, queuing networks, and measuring memory performance of loops. Evaluation of tools is also ongoing by applying them to SciDAC application codes.
The document discusses improving throughput on simultaneous multithreading (SMT) processors by assigning thread priorities based on application signatures. It presents research showing that prioritizing threads based on their usage of processor resources improves throughput for many applications. Application signatures characterize usage of critical resources like floating point and cache units. Microbenchmarks are used to empirically determine optimal priority settings for signature pairs, which can then predict priorities to improve throughput of other applications.
This document discusses application-specific instruction-set processors (ASIPs) for network intrusion detection systems (NIDS). It evaluates the performance of running Snort, an open-source NIDS software, on various microprocessors including V850, OR1K, MIPS32, ARM7TDMI and PowerPC32. Optimization techniques like compiler optimizations can improve performance by up to 30% on some processors. ARM7TDMI performance improved most with offered optimization levels focusing on loops and jumps. ASIPs provide flexibility over ASICs for updating attack signatures. Future work includes optimizing compilers and designing custom processors.
GPCE16: Automatic Non-functional Testing of Code Generators FamiliesMohamed BOUSSAA
The intensive use of generative programming techniques provides an elegant engineering solution to deal with the heterogeneity of platforms and technological stacks. The use of domain-specific languages for example, leads to the creation of numerous code generators that automatically translate high-level system specifications into multi-target executable code. Producing correct and efficient code generator is complex and error-prone. Although software designers provide generally high-level test suites to verify the functional outcome of generated code, it remains challenging and tedious to verify the behavior of produced code in terms of non-functional properties. This paper describes a practical approach based on a runtime monitoring infrastructure to automatically check the potential inefficient code generators. This infrastructure, based on system containers as execution platforms, allows code-generator developers to evaluate the generated code performance. We evaluate our approach by analyzing the performance of Haxe, a popular high-level programming language that involves a set of cross-platform code generators. Experimental results show that our approach is able to detect some performance inconsistencies that reveal real issues in Haxe code generators.
IRJET- Factoid Question and Answering SystemIRJET Journal
This document describes a factoid question answering system that uses neural networks and the Tensorflow framework. The system takes in a text document and question as input. It then processes the input using techniques like gated recurrent units and support vector machines to classify the question. The system calculates attention between facts and the question, modifies its memory, and identifies the word closest to the answer to output as the response. Key aspects of the system include training a question answering engine with Tensorflow, storing and retrieving data, and generating the final answer.
29A Methodology for Testing CPU EmulatorsLORENZO MARTI.docxgilbertkpeters11344
29
A Methodology for Testing CPU Emulators
LORENZO MARTIGNONI, Università degli Studi di Udine
ROBERTO PALEARI, ALESSANDRO REINA, GIAMPAOLO FRESI ROGLIA,
and DANILO BRUSCHI, Università degli Studi di Milano
A CPU emulator is a software system that simulates a hardware CPU. Emulators are widely used by
computer scientists for various kind of activities (e.g., debugging, profiling, and malware analysis). Although
no theoretical limitation prevents developing an emulator that faithfully emulates a physical CPU, writing
a fully featured emulator is a very challenging and error prone task. Modern CISC architectures have a very
rich instruction set, some instructions lack proper specifications, and others may have undefined effects in
corner cases. This article presents a testing methodology specific for CPU emulators, based on fuzzing. The
emulator is “stressed” with specially crafted test cases, to verify whether the CPU is properly emulated or
not. Improper behaviors of the emulator are detected by running the same test case concurrently on the
emulated and on the physical CPUs and by comparing the state of the two after the execution. Differences
in the final state testify defects in the code of the emulator. We implemented this methodology in a prototype
(named as EmuFuzzer), analyzed five state-of-the-art IA-32 emulators (QEMU, Valgrind, Pin, BOCHS, and
JPC), and found several defects in each of them, some of which can prevent proper execution of programs.
Categories and Subject Descriptors: D.2.5 [Software Engineering]: Testing and Debugging; D.2.8
[Software Engineering]: Metrics—Complexity measures, performance measures
General Terms: Reliability, Verification
Additional Key Words and Phrases: Software testing, fuzzing, emulation, automatic test generation
ACM Reference Format:
Martignoni, L., Paleari, R., Reina, A., Roglia, G. F., and Bruschi, D. 2013. A methodology for testing CPU
emulators. 2013 ACM Trans. Softw. Eng. Methodol. 22, 4, Article 29 (October 2013), 26 pages.
DOI: http://dx.doi.org/10.1145/2522920.2522922
1. INTRODUCTION
In Computer Science, the term “emulator” is typically used to denote a piece of soft-
ware that simulates a hardware system [Lichstein 1969]. Different hardware sys-
tems can be simulated: a device [Google Inc. 2011], a CPU (Pin [Luk et al. 2005] and
Valgrind [Nethercote 2004]), and even an entire PC system (QEMU [Bellard 2005],
BOCHS [Lawton 1996], JPC [Preston et al. 2007], and Simics [Magnusson et al. 2002]).
Emulators are widely used today for many applications: development, debugging, pro-
filing, security analysis, etc. For example, the NetBSD AMD64 port was initially devel-
oped using an emulator [netbsd64 2011].
This article is a revised and extended version of the conference paper “Testing CPU Emulators”, presented
at ISSTA 2009.
Authors’ addresses: L. Martignoni, Dipartimento di Fisica, Università degli Studi di Udine, Italy;
email: [email protected]; R. Paleari, A. Reina, G. F. Roglia,.
Guy Leshem provides his curriculum vitae, which details his experience as a software engineer, physicist, and statistician. He has a PhD in statistics from Hebrew University, with a thesis focusing on improving machine learning algorithms. He has over 10 years of experience as a software engineer at Intel developing networking tools. Currently he works as a statistical advisor and has taught university courses.
Guy Leshem provides his curriculum vitae, which details his background as a software engineer, physicist, and statistician. He holds a PhD in statistics from Hebrew University, with a focus on improving machine learning algorithms. He has over 10 years of experience as a software engineer at Intel developing networking tools. Currently he works as a statistical advisor and teaches statistics courses.
Creation of a Test Bed Environment for Core Java Applications using White Box...cscpconf
A Test Bed Environment allows for rigorous, transparent, and replicable testing of scientific
theories. However, in software development these test beds can be specified hardware and
software environment for the application under test. Though the existing open source test bed
environments in Integrated Development Environment (IDE)s are capable of supporting the
development of Java application types, test reports are generated by third party developers.
They do not enhance the utility and the performance of the system constructed. Our proposed
system, we have created a customized test bed environment for core java application programs
used to generate the test case report using generated control flow graph. This can be obtained by developing a new mini compiler with additional features.
A Platform for Accelerating Machine Learning ApplicationsNVIDIA Taiwan
Robert Sheen from HPE gave a presentation on machine learning applications and accelerating deep learning. He provided a quick introduction to neural networks, discussing their structure and how they are inspired by biological neurons. Deep learning requires high performance computing due to its computational intensity during training. Popular deep learning frameworks like CogX were also discussed, which provide tools and libraries to help build and optimize neural networks. Finally, several enterprise use cases for machine learning and deep learning were highlighted, such as in finance, healthcare, security, and geospatial applications.
The field of machine programming — the automation of the development of software — is making notable research advances. This is, in part, due to the emergence of a wide range of novel techniques in machine learning. In today’s technological landscape, software is integrated into almost everything we do, but maintaining software is a time-consuming and error-prone process. When fully realized, machine programming will enable everyone to express their creativity and develop their own software without writing a single line of code. Intel realizes the pioneering promise of machine programming, which is why it created the Machine Programming Research (MPR) team in Intel Labs. The MPR team’s goal is to create a society where everyone can create software, but machines will handle the “programming” part.
Debugging and optimization of multi-thread OpenMP-programsPVS-Studio
The task of familiarizing programmers with the sphere of developing parallel applications is getting more and more urgent. This article is a brief introduction into creation of multi-thread applications based on OpenMP technology. The approaches to debugging and optimization of parallel applications are described.
This presentation by OECD, OECD Secretariat, was made during the discussion “Artificial Intelligence, Data and Competition” held at the 143rd meeting of the OECD Competition Committee on 12 June 2024. More papers and presentations on the topic can be found at oe.cd/aicomp.
This presentation was uploaded with the author’s consent.
Carrer goals.pptx and their importance in real lifeartemacademy2
Career goals serve as a roadmap for individuals, guiding them toward achieving long-term professional aspirations and personal fulfillment. Establishing clear career goals enables professionals to focus their efforts on developing specific skills, gaining relevant experience, and making strategic decisions that align with their desired career trajectory. By setting both short-term and long-term objectives, individuals can systematically track their progress, make necessary adjustments, and stay motivated. Short-term goals often include acquiring new qualifications, mastering particular competencies, or securing a specific role, while long-term goals might encompass reaching executive positions, becoming industry experts, or launching entrepreneurial ventures.
Moreover, having well-defined career goals fosters a sense of purpose and direction, enhancing job satisfaction and overall productivity. It encourages continuous learning and adaptation, as professionals remain attuned to industry trends and evolving job market demands. Career goals also facilitate better time management and resource allocation, as individuals prioritize tasks and opportunities that advance their professional growth. In addition, articulating career goals can aid in networking and mentorship, as it allows individuals to communicate their aspirations clearly to potential mentors, colleagues, and employers, thereby opening doors to valuable guidance and support. Ultimately, career goals are integral to personal and professional development, driving individuals toward sustained success and fulfillment in their chosen fields.
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To Get any Project for CSE, IT ECE, EEE Contact Me @ 09666155510, 09849539085 or mail us - ieeefinalsemprojects@gmail.com-Visit Our Website: www.finalyearprojects.org
Prateep Kumar Sengupta is seeking a position as an engineer where he can contribute his skills in data science, machine learning, and R&D. He has a M.Tech in Communication Engineering and B.Tech in Electronics and Instrumentation Engineering. His skills include Python, UNIX shell scripts, Perl, and tools for data science, machine learning, web scraping, and email marketing. He has work experience in technology roles and has conducted research and published papers in machine learning and antenna optimization.
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1 Exactpro, UK, Georgia, USA, Russia
2 Skolkovo Institute of Science and Technology, Russia
3 Higher School of Economics, Russia
Testing embedded system through optimal mining technique (OMT) based on multi...IJECEIAES
Testing embedded systems must be done carefully particularly in the significant regions of the embedded systems. Inputs from an embedded system can happen in multiple order and many relationships can exist among the input sequences. Consideration of the sequences and the relationships among the sequences is one of the most important considerations that must be tested to find the expected behavior of the embedded systems. On the other hand combinatorial approaches help determining fewer test cases that are quite enough to test the embedded systems exhaustively. In this paper, an Optimal Mining Technique that considers multi-input domain which is based on built-in combinatorial approaches has been presented. The method exploits multi-input sequences and the relationships that exist among multi-input vectors. The technique has been used for testing an embedded system that monitors and controls the temperature within the Nuclear reactors.
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The document discusses improving throughput on simultaneous multithreading (SMT) processors by assigning thread priorities based on application signatures. It presents research showing that prioritizing threads based on their usage of processor resources improves throughput for many applications. Application signatures characterize usage of critical resources like floating point and cache units. Microbenchmarks are used to empirically determine optimal priority settings for signature pairs, which can then predict priorities to improve throughput of other applications.
This document discusses application-specific instruction-set processors (ASIPs) for network intrusion detection systems (NIDS). It evaluates the performance of running Snort, an open-source NIDS software, on various microprocessors including V850, OR1K, MIPS32, ARM7TDMI and PowerPC32. Optimization techniques like compiler optimizations can improve performance by up to 30% on some processors. ARM7TDMI performance improved most with offered optimization levels focusing on loops and jumps. ASIPs provide flexibility over ASICs for updating attack signatures. Future work includes optimizing compilers and designing custom processors.
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29A Methodology for Testing CPU EmulatorsLORENZO MARTI.docxgilbertkpeters11344
29
A Methodology for Testing CPU Emulators
LORENZO MARTIGNONI, Università degli Studi di Udine
ROBERTO PALEARI, ALESSANDRO REINA, GIAMPAOLO FRESI ROGLIA,
and DANILO BRUSCHI, Università degli Studi di Milano
A CPU emulator is a software system that simulates a hardware CPU. Emulators are widely used by
computer scientists for various kind of activities (e.g., debugging, profiling, and malware analysis). Although
no theoretical limitation prevents developing an emulator that faithfully emulates a physical CPU, writing
a fully featured emulator is a very challenging and error prone task. Modern CISC architectures have a very
rich instruction set, some instructions lack proper specifications, and others may have undefined effects in
corner cases. This article presents a testing methodology specific for CPU emulators, based on fuzzing. The
emulator is “stressed” with specially crafted test cases, to verify whether the CPU is properly emulated or
not. Improper behaviors of the emulator are detected by running the same test case concurrently on the
emulated and on the physical CPUs and by comparing the state of the two after the execution. Differences
in the final state testify defects in the code of the emulator. We implemented this methodology in a prototype
(named as EmuFuzzer), analyzed five state-of-the-art IA-32 emulators (QEMU, Valgrind, Pin, BOCHS, and
JPC), and found several defects in each of them, some of which can prevent proper execution of programs.
Categories and Subject Descriptors: D.2.5 [Software Engineering]: Testing and Debugging; D.2.8
[Software Engineering]: Metrics—Complexity measures, performance measures
General Terms: Reliability, Verification
Additional Key Words and Phrases: Software testing, fuzzing, emulation, automatic test generation
ACM Reference Format:
Martignoni, L., Paleari, R., Reina, A., Roglia, G. F., and Bruschi, D. 2013. A methodology for testing CPU
emulators. 2013 ACM Trans. Softw. Eng. Methodol. 22, 4, Article 29 (October 2013), 26 pages.
DOI: http://dx.doi.org/10.1145/2522920.2522922
1. INTRODUCTION
In Computer Science, the term “emulator” is typically used to denote a piece of soft-
ware that simulates a hardware system [Lichstein 1969]. Different hardware sys-
tems can be simulated: a device [Google Inc. 2011], a CPU (Pin [Luk et al. 2005] and
Valgrind [Nethercote 2004]), and even an entire PC system (QEMU [Bellard 2005],
BOCHS [Lawton 1996], JPC [Preston et al. 2007], and Simics [Magnusson et al. 2002]).
Emulators are widely used today for many applications: development, debugging, pro-
filing, security analysis, etc. For example, the NetBSD AMD64 port was initially devel-
oped using an emulator [netbsd64 2011].
This article is a revised and extended version of the conference paper “Testing CPU Emulators”, presented
at ISSTA 2009.
Authors’ addresses: L. Martignoni, Dipartimento di Fisica, Università degli Studi di Udine, Italy;
email: [email protected]; R. Paleari, A. Reina, G. F. Roglia,.
Guy Leshem provides his curriculum vitae, which details his experience as a software engineer, physicist, and statistician. He has a PhD in statistics from Hebrew University, with a thesis focusing on improving machine learning algorithms. He has over 10 years of experience as a software engineer at Intel developing networking tools. Currently he works as a statistical advisor and has taught university courses.
Guy Leshem provides his curriculum vitae, which details his background as a software engineer, physicist, and statistician. He holds a PhD in statistics from Hebrew University, with a focus on improving machine learning algorithms. He has over 10 years of experience as a software engineer at Intel developing networking tools. Currently he works as a statistical advisor and teaches statistics courses.
Creation of a Test Bed Environment for Core Java Applications using White Box...cscpconf
A Test Bed Environment allows for rigorous, transparent, and replicable testing of scientific
theories. However, in software development these test beds can be specified hardware and
software environment for the application under test. Though the existing open source test bed
environments in Integrated Development Environment (IDE)s are capable of supporting the
development of Java application types, test reports are generated by third party developers.
They do not enhance the utility and the performance of the system constructed. Our proposed
system, we have created a customized test bed environment for core java application programs
used to generate the test case report using generated control flow graph. This can be obtained by developing a new mini compiler with additional features.
A Platform for Accelerating Machine Learning ApplicationsNVIDIA Taiwan
Robert Sheen from HPE gave a presentation on machine learning applications and accelerating deep learning. He provided a quick introduction to neural networks, discussing their structure and how they are inspired by biological neurons. Deep learning requires high performance computing due to its computational intensity during training. Popular deep learning frameworks like CogX were also discussed, which provide tools and libraries to help build and optimize neural networks. Finally, several enterprise use cases for machine learning and deep learning were highlighted, such as in finance, healthcare, security, and geospatial applications.
The field of machine programming — the automation of the development of software — is making notable research advances. This is, in part, due to the emergence of a wide range of novel techniques in machine learning. In today’s technological landscape, software is integrated into almost everything we do, but maintaining software is a time-consuming and error-prone process. When fully realized, machine programming will enable everyone to express their creativity and develop their own software without writing a single line of code. Intel realizes the pioneering promise of machine programming, which is why it created the Machine Programming Research (MPR) team in Intel Labs. The MPR team’s goal is to create a society where everyone can create software, but machines will handle the “programming” part.
Debugging and optimization of multi-thread OpenMP-programsPVS-Studio
The task of familiarizing programmers with the sphere of developing parallel applications is getting more and more urgent. This article is a brief introduction into creation of multi-thread applications based on OpenMP technology. The approaches to debugging and optimization of parallel applications are described.
Similar to PhD Defense Slides - Automatic Non-functional Testing and Tuning of Configurable Generators (20)
This presentation by OECD, OECD Secretariat, was made during the discussion “Artificial Intelligence, Data and Competition” held at the 143rd meeting of the OECD Competition Committee on 12 June 2024. More papers and presentations on the topic can be found at oe.cd/aicomp.
This presentation was uploaded with the author’s consent.
Carrer goals.pptx and their importance in real lifeartemacademy2
Career goals serve as a roadmap for individuals, guiding them toward achieving long-term professional aspirations and personal fulfillment. Establishing clear career goals enables professionals to focus their efforts on developing specific skills, gaining relevant experience, and making strategic decisions that align with their desired career trajectory. By setting both short-term and long-term objectives, individuals can systematically track their progress, make necessary adjustments, and stay motivated. Short-term goals often include acquiring new qualifications, mastering particular competencies, or securing a specific role, while long-term goals might encompass reaching executive positions, becoming industry experts, or launching entrepreneurial ventures.
Moreover, having well-defined career goals fosters a sense of purpose and direction, enhancing job satisfaction and overall productivity. It encourages continuous learning and adaptation, as professionals remain attuned to industry trends and evolving job market demands. Career goals also facilitate better time management and resource allocation, as individuals prioritize tasks and opportunities that advance their professional growth. In addition, articulating career goals can aid in networking and mentorship, as it allows individuals to communicate their aspirations clearly to potential mentors, colleagues, and employers, thereby opening doors to valuable guidance and support. Ultimately, career goals are integral to personal and professional development, driving individuals toward sustained success and fulfillment in their chosen fields.
XP 2024 presentation: A New Look to Leadershipsamililja
Presentation slides from XP2024 conference, Bolzano IT. The slides describe a new view to leadership and combines it with anthro-complexity (aka cynefin).
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This presentation was uploaded with the author’s consent.
This presentation by Nathaniel Lane, Associate Professor in Economics at Oxford University, was made during the discussion “Pro-competitive Industrial Policy” held at the 143rd meeting of the OECD Competition Committee on 12 June 2024. More papers and presentations on the topic can be found at oe.cd/pcip.
This presentation was uploaded with the author’s consent.
This presentation by Thibault Schrepel, Associate Professor of Law at Vrije Universiteit Amsterdam University, was made during the discussion “Artificial Intelligence, Data and Competition” held at the 143rd meeting of the OECD Competition Committee on 12 June 2024. More papers and presentations on the topic can be found at oe.cd/aicomp.
This presentation was uploaded with the author’s consent.
Collapsing Narratives: Exploring Non-Linearity • a micro report by Rosie WellsRosie Wells
Insight: In a landscape where traditional narrative structures are giving way to fragmented and non-linear forms of storytelling, there lies immense potential for creativity and exploration.
'Collapsing Narratives: Exploring Non-Linearity' is a micro report from Rosie Wells.
Rosie Wells is an Arts & Cultural Strategist uniquely positioned at the intersection of grassroots and mainstream storytelling.
Their work is focused on developing meaningful and lasting connections that can drive social change.
Please download this presentation to enjoy the hyperlinks!
Mastering the Concepts Tested in the Databricks Certified Data Engineer Assoc...SkillCertProExams
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This presentation was uploaded with the author’s consent.
This presentation by OECD, OECD Secretariat, was made during the discussion “Competition and Regulation in Professions and Occupations” held at the 77th meeting of the OECD Working Party No. 2 on Competition and Regulation on 10 June 2024. More papers and presentations on the topic can be found at oe.cd/crps.
This presentation was uploaded with the author’s consent.
7. 2
1
Automatic code generation
7
Machine Code
C Code
a highly configurable process
Variants
Optimisation flags
(e.g., CFLAGS)
HAXE programs
GPLsGPLs
Variants
-Os
-ftree-vectorize
-Og
-O3
-Ofast
-O2
8. Automatic code generation
8
a highly configurable process
2
1
GPLs
High-level
program specifica^on
Templates
Configurations
Files Flags
Generated code must be effectively tested
Generators
9. Automatic code generation
9
a highly configurable process
2
1
GPLs
High-level
program specifica^on
Templates
Configurations
Files Flags
Tests pass: no bugs in generators
Generators
I will never write
code again !
10. Automatic code generation
10
a highly configurable process
2
1
GPLs
High-level
program specifica^on
Templates
Configurations
Files Flags
Tests fail: bugs must be fixed !
Generators
I will never use
generators again !
11. Automatic code generation
11
a highly configurable process
2
1
GPLs
High-level
program specifica^on
Templates
Configurations
Files Flags
Tests pass, but what about the non-functional properties (quality) of generated code ?
Generators
It is too slow !
I am running out
of memory
14. Related work
14
¤ Tes5ng generators
• Func^onal tes^ng: executable models, differen^al tes^ng [Conrad et al. ’10, Stuermer et al. ’07]
Do not address the NF proper^es
¤ Auto-tuning generators:
• Auto-tuning: a mono objec^ve op^miza^on [Bashkansky et al. ’07, Stephenson et al. ’03]
• Phase ordering problem [Kulkarni et al. ‘06, Cooper et al. ’99]
• Predic^ng op^miza^ons: a machine learning op^miza^on [Fursin et al. 11’]
• Conflic^ng objec^ves: a mul^-objec^ve op^miza^on [Hoste et al. 08’, Mar^nez et al. ’14]
Do not exploit recent advances in SBSE (e.g., diversity-based explora^on)
14
16. 16
Contribution II:
An auto-tuning approach
Contribution I:
An automatic non-functional
testing approach
Select the best
configuration
Generator
experts
Build/maintain
Genrerator
users
Identify code
generator issues
Contribution III:
A lightweight environment for monitoring
and testing the generated code
Use/configure
21. Leveraging metamorphic testing to
automatically detect inconsistencies
Metamophic tes5ng1 (MT):
- Oracles can be derived from proper^es of the system under test
- Exploit the rela^on between the inputs and outputs of special test cases of the system
under test to derive metamorphic rela^ons (MRs) defined as test oracles for new test
cases
21
Metamorphic
Rela5on
Derive
21
21
Original test cases Outputs
Verify New test cases Outputs
21
1Chen et al., Metamorphic tes^ng: a new approach for genera^ng next
test cases, University of Science and Technology, Hong Kong, 1998.
23. Statistical methods
o We propose two varia^on analysis approaches to define the threshold value
23
23
23
R-Chart (Range Chart) PCA (Principal Component Analysis)
Ø A mul^variate sta^s^cal approach
Ø Reduce the dimensionality of the original data to a two
dimensions (PC1 & PC2)
Ø A score distance SD measures how far an observa^on
lies from the rest of the data within the PCA subspace
Ø SD with cutoff value higher than 97.5%-Quan^le Q of the
Chi-square distribu^on are detected as outliers
Ø Evaluate the varia^on as a Range R (Max - Min)
Ø Control limits (LCL and UCL) represent the limits
of varia^on that should be expected from a
process
LCL < R < UCL T <
23
30. Analysis
30
v For Core_TS4 in PHP:
• We observe the intensive use of « arrays »
• Arrays in PHP are allocated dynamically, leading to a slower wr^ng
speed
• We replace « arrays » by « SplFixedArray »
⇒ Speedup x5
⇒ Memory usage reduc^on x2
⇒ Issue fixed by the Haxe community
Key findings:
- The lack of use of specific types that exist in the standard library shows a real
impact on the non-func^onal behavior of generated code.
30
31. Conclusion
§ A non-functional metamorphic relation is used to detect code generator
inconsistencies
− Two statistical methods are applied to find the right MR definition
§ The evaluation results show that:
− 11 performance and 15 memory usage inconsistencies, violating the
metamorphic relation for Haxe code generators
− The analysis of test suites triggering the inconsistencies shows that there
exist potential issues in some code generators, affecting the quality of
delivered software
31
34. Motivating example
¤ GCC 4.8.4:
- 78 optimizations
- 278 combina^ons
34
Speedup,
Memory,
etc.
Resource
Constraints
WHY
ALWAYS
ME !!
-BOSS: Clients complain about the high
memory consumption
-BOSS: Is it possible to consume less
CPU?
we don’t have enough resources/money
-BOSS: Please, can we optimize even
more ?
Good luck Son !!
34
- Tes^ng each op^miza^on configura^on is impossible
- Heuris^cs are needed
34
34
35. Compiler auto-tuning is complex
35
¤ Construc^ng a good set of op^miza^on levels (-Ox) is hard
• Conflic^ng objec^ves
• Complex interac^ons
• Unknown effect of some op^miza^ons
35 35
40. RQ1- Results
RQ1: Mono-objec5ve SBSE Valida5on.
- Training set: 10 Csmith programs
- Average S, MR, and CR
- Comparison: Ox, RS, GA and NS
Key findings for RQ1:
– Best discovered op^miza^on sequences using mono-objec^ve search techniques always provide beber results than
standard GCC op^miza^on levels.
– Novelty Search is a good candidate to improve code in terms of non-func^onal proper^es since it is able to discover
op^miza^on combina^ons that outperform RS and GA.
Search for best op^miza^on
sequence
Best
sequence
Op^miza^ons
Non-func^onal
Metric
Training set programs
4040
43. RQ4- Results
RQ4: Trade-offs between non-func5onal proper5es.
- 1 Csmith program
- Trade-off <execu^on ^me-memory usage>
Key findings for RQ4:
– NOTICE is able to construct op^miza^on levels that represent op^mal trade-offs between non-func^onal
proper^es.
– NSGA-II performs beber than our NS adapta^on for mul^-objec^ve op^miza^on. However, NS-II performs clearly
beber than standard GCC op^miza^ons and previously discovered sequences in RQ1.
43
Op^miza^ons Pareto front
solu^ons
Mul^-objec^ve search
Trade-off ^me/memory
Input program
Pareto front NS-II
(mul^-objec^ve)
Ofast
O3
O2
O1
Best CPU reduc^on
(mono-objec^ve)
Best memory reduc^on
(mono-objec^ve)
Pareto front NSGA-II
(mul^-objec^ve)
43
44. Conclusion
§ Novel formulation of the compiler optimization problem based on Novelty
Search
§ Novelty Search is able to generate effective optimizations
− Generated sequeces perform better than standard levels
− Our approach outperfroms classical approaches (GA and RS)
§ Trade-offs between non-functional properties are constructed
− NSGA-II performs better than NS and mono-objective approaches
44
47. Infrastructure Overview
47
¤ We propose:
• A micro-service infrastructure, based on system containers (Docker) as execu^on
pla]orms, that allow generator experts/users to evaluate the non-func^onal
proper^es of generated code
47
RuntimeMonitoringEngine
Container C
Container B
Container A
SUT
SUT
SUT
Generate
Generate
Generate
Code
Generator A
Code
Generator B
Code
Generator C
Code Generation Runtime monitoring engineCode Execution
Container A’
Container B’
Container C’
Footprint C’
Footprint A’
HTTP
requests
Footprint B’Request
Resource usage extraction
Resource usage
DB
50. Conclusion
§ Effective support for automatically deploying, executing, and testing the
generated code in different environment settings
§ The conducted experiments showed the usefulness of this infrastructure for
tuning and testing generators
50
52. 52
Generator
experts
Genrerator
users
Build and maintain
I can now easily
determine the best
configuration settings
for my generator
I am now able to
automa5cally test my
code generator family
in terms of NFP
Conclusion
Effective support for testing and resource
usage monitoring
Use and configure
53. Perspectives
53
v Combine the proposed black-box approach with tracability tools:
• Tracking the source of code generator inconsistencies
v Speed up the ^me required to tune and test generators:
• Deploy tests on many nodes in the cloud using mul^ple containers in parallel
v Automa^c test case genera^on:
• Test amplifica^on
• Evaluate the quality of executed tests (e.g., code coverage)
v Improve the auto-tuning approach:
• Evaluate other compilers (e.g., LLVM, Clang)
• Explore more tradeoffs among resource usage metrics
• Evaluate different hardware se}ngs
54. Publications
• Mohamed Boussaa, Olivier Barais, Benoit Baudry, Gerson Sunyé: Automa5c Non-func5onal Tes5ng of
Code Generators Families. In The 15th Interna^onal Conference on Genera^ve Programming: Concepts &
Experiences (GPCE 2016), Amsterdam, Netherlands, October 2016.
• Mohamed Boussaa, Olivier Barais, Benoit Baudry, Gerson Sunyé: NOTICE: A Framework for Non-
func5onal Tes5ng of Compilers. In 2016 IEEE Interna^onal Conference on So[ware Quality, Reliability &
Security (QRS 2016), Vienna, Austria, August 2016.
• Mohamed Boussaa, Olivier Barais, Benoit Baudry, Gerson Sunyé: A Novelty Search-based Test Data
Generator for Object-oriented Programs. In Gene^c and Evolu^onary Computa^on Conference
Companion (GECCO 2015), Madrid, Spain, July 2015.
• Mohamed Boussaa, Olivier Barais, Benoit Baudry, Gerson Sunyé: A Novelty Search Approach for
Automa5c Test Data Genera5on. In 8th Interna^onal Workshop on Search-Based So[ware Tes^ng
(SBST@ICSE 2015), Florence, Italy, May 2015.
Under review:
• Mohamed Boussaa, Olivier Barais, Benoit Baudry, Gerson Sunyé: Leveraging Metamorphic Tes5ng to
Automa5cally Detect Inconsistencies in Code Generator Families. IEEE Transac^ons on Reliability, August
2017.
54
58. NSGA-II overview (I)
58
• NSGA-II: Non-dominated Sorting Genetic Algorithm (K. Deb et al., ’02)
Parent
Population
Offspring
Population
Non-dominated
sorting
F1
F2
F3
F4
Crowding distance
sorting
Population in
next
generation
MOEA Framework hbp://moeaframework.org/