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  1. 1. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com UNIT IV-FINITE STATE MACHINES (FSM) INTRODUCTION: A state machine is a digital circuit that relies not only on the circuit's inputs, but also the current state of the system to determine the proper output. So, a state machine is similar to a sequential logic circuit whose output depend not only on the present inputs but also present state of the system. In a state machine, if the number of states are finite such a machine is popularly known as Finite State Machine(FSM) For example, assume that an elevator is stopped on the eighth floor and someone from the fourth floor presses the elevator call button. The elevator needs to decide whether to go up or down. As long as it remembers its current state, i.e., that it is on the eighth floor, it will know that it needs to go down to access the fourth floor. There are two types of state machines. (i) Moore State Machine and (ii)Mealy State Machine The state machine whose output depends only on the current state is known as Moore Machine. The Mealy machine is one whose output is based on both the current state of the machine and the system's input. Finite-state machines, also called finite-state automata (singular: automaton) or just finite automata are much more restrictive in their capabilities than Turing machines. Significance of FSM: Improper designs of an FSM can lead to the presence of logic noise in output signals and this noise can cause the erroneous triggering of a next stage switching device to which the FSM is connected.So,it may be important that FSMs be designed to issue signals which are free of unwanted logic transients(noise) called glitches. A glitch is an unwanted transient in an otherwise steady state signal and may appear as either a logic 0 -1-0 (positive glitch) or as a logic 1-0-1 (negative) glitch as shown below. 1
  2. 2. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com A glitch that occurs as a result of two or more state variable changes during a state-to state transition is called an output race glitch or simply ORG .So,an ORG may be regarded as an internally initiated function hazard. STATE DIAGRAMS : The State diagram models a state machine by using circles to represent each of the possible states and arrows to represent all of the possible transitions between the states. Let us consider the example below. The upper half of each circle indicates the name of the state. The lower half indicates the binary output associated with that state. In the case of the light bulb state machine, a zero is output while we are in the OFF state and a one is output while we are in the ON state. The arrows along with the input value say that when we are in state OFF and the switch input goes to a 1, move to state ON. When we are in state ON and the switch input goes to a 0, move to state OFF. Let's design a 3-bit up/down binary counter as a state machine. The block diagram of the counter is shown below. One of the inputs to this counter is a clock. In general many state machines have a clock. It is used to drive the system from one state to the next. To do this, it is connected to the clock input of the latches. When a pulse is received, the next state is stored in the latches where it becomes the current state. The other input to our system is direction. The direction signal is a binary input to indicate the system whether the stored value is to be incremented or decremented. 2
  3. 3. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com [ Normally when direction bit is 0 we will be decrementing and when direction bit is 1 we will be incrementing]. There is an additional important information that must be represented with a state diagram. When a system first powers up, it should be initialized to a reset state. We need to indicate on the diagram which state is defined as the initial state A 3-bit counter has an output that is a three-bit number. Every time a clock pulse occurs, the counter will change state to either increment or decrement the output depending on the value of direction. For example, if direction equals one, then each clock pulse will increment the output through the sequence 000, 001, 010, 011, 100, 101, 110, 111, 000, 001, etc. If direction equals zero, then the output will decrement once for each clock pulse, i.e., 000, 111, 110, 101, 100,011, 010, 001, 000, 111, 001, etc. The arrows going clockwise around the inside of the diagram represent the progression through the states at each clock pulse when direction equals 1. The arrows going counter clockwise around the outside of the diagram represent the progression through the states at each clock pulse when direction equals zero. Parity Checker: The parity checker is a simple logic circuit which has one input , and one output in addition to a clock input. This is a simple sequential circuit or FSM. When a sequence of 0‟s and 1‟s is applied to the X input, the output of the circuit should be (Z) = 1 if the total number of 1 inputs received is odd ; that is, the output should be 1 if the input parity is odd. Thus, if data which originally had odd parity is transmitted to the circuit, a final output of 3
  4. 4. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Z = 0 indicates that an error in transmission has occurred. The value of X is read at the time of the active clock edge. The X input must be synchronized with the clock so that it assumes its next value before the next active clock edge. The clock input is necessary in order to distinguish consecutive 0‟s or consecutive 1‟s on the X input. Let us consider the state graph shown below. The sequential circuit has only two states S0 and S1, corresponding respectively to an even number of 1‟s received and an odd number of 1‟s received. The graph start with the state S0 because initially zero 1‟s have been received, and zero is an even number. As shown in state graph , if the circuit is in state S0 (even number of 1‟s received) and X = 0 is received, the circuit must stay in S0 because the number of 1‟s received is still even. However, if X = 1 is received, the circuit goes to state S1 because the number of 1‟s received is then odd. Similarly, if the circuit is in state S1 (odd number of 1‟s received) a 0 input causes no state change, but a 1 causes a change to S0 because the number of 1‟s received is then even. The output Z should be 1 whenever the circuit is in state S1 (odd number of 1‟sreceived). The output is listed below the state on the state graph. State Table: The state table specifies the next state and the output of a sequential circuit interms of present state and inputs. The state table for the parity checker is shown below.As there are only two states ,it can be implemented using only one flip-flop. Present State Next State X=0 Present Output X=1 4
  5. 5. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com S0 S0 S1 0 S1 S1 S0 1 We will let Q = 0 correspond to state S0 and Q = 1 correspond to S1. We can then set up a table which shows the next state of flip-flop Q as a function of the present state and X. Basic Circuit Organization: The block diagram of the Finite state machine circuitry is shown below.It has three blocks .(i) The logic determining circuit of the next state (ii) Latches and (iii) Logic circuit determining the output from the current state. The center block of the block diagram consists of Latches. This component of the system consists of one or more D latches, the combined outputs of which represent the current state of the state machine. The inputs to the latches represent what the next state would be if the clock were to pulse at that particular moment. The number of latches in this portion of the circuit is based on the number of states the system can have. 5
  6. 6. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com If, for example, a state diagram is designed with ten states for a system, then we would have to have enough latches so that their outputs, Q, could represent at least ten different patterns of ones and zeros. By numbering the ten states in binary, 0, 1, 10, 11, 100, 101, 110, 111, 1000, 1001, we see that we will need at least four latches, the number of digits it takes to represent the highest value, 1001. The D inputs serve to hold the binary value of the next state that the latches, and hence the state machine, will be set to. When a clock pulse occurs, the next state is stored in the latches making it the current state. The leftmost block in the block diagram represents the digital logic used to determine the next state of the system. It determines this from the inputs to the system and the current state of the system. The rightmost block in the block diagram denotes the digital logic used to determine the output of the system based on its current state. Mealy sequential circuit : The diagram below shows general model for a clocked Mealy sequential circuit with m inputs, n outputs, and k clocked D flip-flops used as memory. Here the presence of feedback in the sequential circuit is important as the flip-flop outputs are fedback as inputs to the combinational sub circuit. The combinational subcircuit realizes the n output functions and the k next-state functions, which serve as inputs to the D flip-flops: Z1 = f1(X1, X2, . . . , Xm, Q1, Q2, . . . , Qk) Z2 = f2(X1, X2, . . . , Xm, Q1, Q2, . . . , Qk) . . . n-output functions . . Zn = fn(X1, X2, . . . , Xm, Q1, Q2, . . . , Qk) similarly Q1+ = D1 = g1(X1, X2, . . . , Xm, Q1, Q2, . . . , Qk) Q2+ = D2 = g2(X1, X2, . . . , Xm, Q1, Q2, . . . , Qk . . . k-next state functions . + Qk = Dk = gk(X1, X2, . . . , Xm, Q1, Q2, . . . , Qk 6
  7. 7. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com When a set of inputs is applied to the circuit, the combinational subcircuit generates the outputs (Z1, Z2, . . . , Zn) and the flip-flop inputs (D1, D2, . . . , Dk). Then, a clock pulse is applied and the flip-flops change to the proper next state. This process is repeated for each set of inputs. At a given point in time, the outputs of the flip-flops represent the present state of the circuit (Q1, Q2, . s. . , Qk). These Qi‟s feed back into the combinational circuit, which generates the flip-flop inputs using the Qi‟s and the X inputs. When D flip-flops are used, Di = Q+i therefore, the combinational circuit outputs are labeled Q+1 , Q+2 , etc. The clock synchronizes the operation of the flip-flops and prevents timing problems.The gates (or other logic) in the combinational sub circuit have finite propagation delays, so when the inputs to the circuit are changed, a finite time is required before the flip-flop inputs reach their final values. Because the gate delays are not all the same, the flip-flop input signals may contain transients, and they may change at different times. If the next active clock edge does not occur until all flip-flop input signals have reached their final steady-state values, the unequal gate 7
  8. 8. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com delays will not cause any timing problems. All flip-flops which must change state do so at the same time in response to the active edge of the clock. When the flip-flops change state, the new flip-flop outputs are fed back into the combinational sub circuit. However, no further change in the flip-flop states can occur until the next clock pulse. State Assignment : The first step in designing the circuit is to derive a state table using suitable methods. Before realizing the state table using flip-flops and logic gates, reduction of the state table to a minimum number of states is desirable. In general, reducing the number of states in a table will reduce the amount of logic required, and the number of flip-flops may also be reduced. For example, if a table with nine states is reduced to eight states, the number of flip-flops required isreduced from four to three, with a possible corresponding reduction in the amount of input logic for the flip-flops. If the table is further reduced to six states, three flip-flops are still required, but the presence of more don‟t-cares in the flip-flop input equations will further reduce the required logic. Afyter reducing the state table, the next step in synthesizing the circuit is to assign binary flip-flop states to the corresponding circuit states. This methodology is known as state assignment. The way in which this assignment is made will determine the amount of logic required for the circuit. The problem of finding a good state assignment which leads to an economical circuit is always a difficult task. The cost of the logic required to realize the sequential circuit is strongly dependent on the way the state assignment is made.There are many methods for the state assignment.They are Trial &Error method and Guidelines based method etc. The trial and error method is useful for only circuits having small number of states . The guidelines based method work well for D-Flip-flops and JK-Flip-flops. They do not work well for T and RS flip-flops. So,one-hot encoding is used for state assignment problem. One-Hot Encoding: In the one-hot encoding (OHE) only one bit of the state variable is “1” or “hot” for any given state. All other state bits are zero. Therefore, one flip-flop (register) is used for every state in the machine i.e. n states uses n flip-flops. Using one-hot encoding, the next-state equations can be derived easily from state diagrams. 8
  9. 9. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com State decoding is simplified, since the state bits themselves can be used directly to indicate whether the machine is in a particular state. In addition, with a one-hot encoded state machine, the inputs to the state bits are often simply the functions of other state bits FPGAs are programmable logic devices that are rich in flip-flops and poor in combo logic. OneHot state machines use one flip-flop per state and thus need much less decode logic. This makes one-hot encoding more efficient for FPGAs. One-hot state machines use one flop per state. The One-Hot encoding for a 5 state variables is shown below in table. State State Variables One-Hot Code S0 S1 S2 S3 S4 Binary Code 00001 00010 00100 01000 10000 Gray Code 000 001 010 011 100 000 001 011 010 110 One-hot encoding (OHE) is better suited for use with the fan-in limited and flip-flop-rich architectures of the higher gate count filed-programmable gate arrays (FPGAs), such as offered by Xilinx, Actel, and others. OHE maps very easily in these architectures. One-hot state machines are typically faster. Speed is independent of the number of states, and instead depends only on the number of transitions into a particular state. FPGA have plenty of registers but the LUTs are limited to few bits wide. One-hot increases the flip-flop usage (one per state) and decreases the width of combinatorial logic. It makes it easy to decode the next state, resulting in large FSMs. And finally, since one hot code state assignment reduces the area (area optimization) by using less logic gates, it consumes less power. There are numerous advantages to using the one hot design methodology : • Maps easily into register-rich FPGA architectures such as QuickLogic and Xilinx. • One-hot state machines are typically faster. Speed is independent of the number of states, and instead depends only on the number of transitions into a particular state. A highly-encoded machine may slow dramatically as more states are added. 9
  10. 10. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com • Don‟t have to worry about finding an "optimal" state encoding. This is particularly beneficial as the machine design is modified, for what is "optimal"for one design may no longer be best if you add afew states and change some others. One-hot is equally "optimal" for all machines. • One-hot machines are easy to design. Schematics can be captured and HDL code can be written directly from the state diagram without coding a state table. • Modifications are straightforward. Adding and deleting states, or changing excitation equations, can be implemented easily without affecting the rest of the machine. • Easily synthesized from VHDL or Verilog. • There is typically no area penalty over highly encoded machines. • Critical paths are easy to find using static timing analysis. • Easy to debug. Bogus state transitions are obvious, and current state display is trivial. Using a One-Hot State Assignment : In designing with CPLDs and FPGAs , it is considered that each logic cell contains one or more flip-flops. These flip-flops are there whether we use them or not. This means that it may not be important to minimize the number of flip-flops used in the design. Instead, we should try to reduce the total number of logic cells used and try to reduce the interconnections between cells. When several cells are cascaded to realize a function the propagation delay is increased and the logic runs slower. In order to design faster logic, we should try to reduce the number of cells required to realize each equation. The one-hot state assignment help to solve this. The one-hot assignment uses one flip-flop for each state, so a state machine with N states requires N flip-flops. Exactly one of the flip-flops is set to one (Hot) in each state and all others are rest. Foe example let us consider the implementation of an LUT in FPGA device . The output of the LUT can be written as 10
  11. 11. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com F= a‟b‟c‟d‟ + a‟b‟c‟d + a‟bcd + ab‟c‟d + ab‟cd‟ +----------------------+ abcd Here each one of the term requires one function generator. If we use one-Hot assignment , the system with four states a,b,c,d (S0, S1, S2, and S3) could use four flip-flops (Q0, Q1, Q2, and Q3) with the following state assignment . S0 : Q0 Q1 Q2 Q3 = 1000 , S1: Q0 Q1 Q2 Q3 = 0100 , S2 : Q0 Q1 Q2 Q3 = 0010 and , S3 : Q0 Q1 Q2 Q3 = 0001 the remaining 12 combinations are not considered. The next-state and output equations are written by inspecting the state graph. Consider the partial state graph given in Figure below. In the graph all the four arcs lead into S3, so,there are four conditions under which the next state is S3. These conditions are Present state (PS) = S0 and X1 = 1, PS = S1 and X2 = 1, PS = S2 and X3 = 1, PS = S3 and X4 = 1. The next state of flip-flop Q3 is 1 under these four conditions (and 0 otherwise). Therefore, the next-state equation for Q3 can be written as Q+3 = X1 (Q0 Q1′ Q2′ Q3′ ) + X2 (Q0′ Q1 Q2′ Q3′) +X3 (Q0 ′ Q1′ Q2 Q3′ ) + X4 (Q0′ Q1′ Q2′ Q3 ) Here as Q0 = 1 means Q1 = Q2 = Q3 = 0, and the Q1 ′ Q2′ Q3′ term is redundant and so it can be eliminated. Similarly, all of the primed state variables can be eliminated from the other terms, so the next-state equation reduces to Q+3 = X1Q0 + X2Q1 + X3Q2 + X4Q3 11
  12. 12. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com In general, when a one-hot state assignment is used, each term in the next-state equation for each flip-flop contains exactly one state variable, and the reduced equation can be written by inspecting the state graph. Similarly, each term in each reduced output equation contains exactly one state variable. Because Z1 = 1 when PS = S0 and X1 = 1, and also when PS = S2 and X3 = 1, we can write that Z1 = X1Q0 + X3Q2. By inspecting the state graph, we can also write that Z2 = X2Q1 + X4Q3 When a one-hot assignment is used, resetting the system requires that one flip flop be set to 1 instead of resetting all flip-flops to 0. If the flip-flops used do not have a preset input, then we can modify the one-hot assignment by replacing Q0 with Q0′ throughout. The assignments for this are S0 : Q0 Q1 Q2 Q3 = 0000, S1 : Q0 Q1 Q2 Q3 = 1100, S2: Q0 Q1 Q2 Q3 = 1010, S3: Q0 Q1 Q2 Q3 = 1001 And the modified equations are Q3+ = X1Q0′ + X2Q1 + X3Q2 + X4Q3 Z1 = X1Q0′ + X3Q2, Z2 = X2Q1 + X4Q3 While designing with CPLDs or FPGAs, one should try both an assignment with a minimum number of state variables and a one-hot assignment to check which one leads to a design with the smallest number of logic cells. Alternatively, if the speed of operation is important, the design which leads to the fastest logic should be chosen. When a one-hot assignment is used, more next-state equations are required, but for some state graphs both the next-state and output equations may contain fewer variables. An equation with fewer variables may require fewer logic cells to realize. The more cells which are cascaded, the longer the propagation delay, and the slower the operation. 12
  13. 13. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com STATE ASSIGNMENTFOR FPGAs: Normally minimum length encodings are preferred because minimu length encodings use minimum number of Flip-Flops. But another important consideration is ,the encoding portion of the combinational logic typically require higher fan-in than the decoding portion.The situation in the assignment of values to the states FSM targeted for FPGAs is different. For example each CLB of the Xilinx XC3000 FPGA has two flip-flops and one look-up table. All the flip-flops are built into the device so,it is a matter of configuring the device to use the flip-flops. According to Chan the -1 option of mustang is the best option for XC3000 series Xilinx FPGAs.This is the one-hot encoding (also known as bit per state –BPS) scheme with the number of flip-flops used is equal to the number of states.In other words ,there is exactly one bit that is ON in each encoded state .The Actel FPGA design also use one-hot encoding for FSMs targeted for Actel FPGAs. Contrary to minimum length encoded FSMs ,the combinational logic of a one-hot – encoded FSM does not contain any encoding logic. Hence the fan-in requirement of one-hot encoded FSMs might be lower than their minimum length encoded counterparts..Low fan-in requirement is important to any to any FPGA implementation, because the number of input pins to FPGA basic cells are bounded. There are certain objections to the one hot scheme of encoding .i.e the number of flip-flops used must be certainly higher than those minimum length encoding schemes. According to „Unger‟,it is a common belief that the cost in logic complexity of one-hot encoding is usually somewhat higher than for other methods. More over because transitions in one –hot encoding are all two-step,it leads to circuits slower than those built employing a single – transition time-assignment. From a timing stand point ,a one hot encoded FSM has the disadvantage that exactly two bits are changed during each state transition. If the propagation delay of these two signals are significantly different ,this would create troublesome hazards or glitches.Another important problem is that ,the designer has only limited control over technology mapping .placement and routing during implementation.This makes the propagation delays rather difficult to control. Problem of the Initial State Assignment for ONE-HOT ENCODING: In Xilinx FPGA devices (Like XC2000,XC3000..) all the flip-flops are cleared after configuration. This means that the value of the initial state of an FSM is all zero.But in one Hot 13
  14. 14. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com Encoding scheme ,every state has exactly 1 ,hence a one hot encoded FSM will be in an illegal state after configuration.This is the actual problem of initial state assignment. References: 1.Fundamentals of Logic Design - Charles H Roth 2.Digital Design using Field Programmable Gtae Arrays –Pak K.Chan & S.Mourad 14