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# UNIT-IV .FINITE STATE MACHINES

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### UNIT-IV .FINITE STATE MACHINES

1. 1. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com UNIT IV-FINITE STATE MACHINES (FSM) INTRODUCTION: A state machine is a digital circuit that relies not only on the circuit's inputs, but also the current state of the system to determine the proper output. So, a state machine is similar to a sequential logic circuit whose output depend not only on the present inputs but also present state of the system. In a state machine, if the number of states are finite such a machine is popularly known as Finite State Machine(FSM) For example, assume that an elevator is stopped on the eighth floor and someone from the fourth floor presses the elevator call button. The elevator needs to decide whether to go up or down. As long as it remembers its current state, i.e., that it is on the eighth floor, it will know that it needs to go down to access the fourth floor. There are two types of state machines. (i) Moore State Machine and (ii)Mealy State Machine The state machine whose output depends only on the current state is known as Moore Machine. The Mealy machine is one whose output is based on both the current state of the machine and the system's input. Finite-state machines, also called finite-state automata (singular: automaton) or just finite automata are much more restrictive in their capabilities than Turing machines. Significance of FSM: Improper designs of an FSM can lead to the presence of logic noise in output signals and this noise can cause the erroneous triggering of a next stage switching device to which the FSM is connected.So,it may be important that FSMs be designed to issue signals which are free of unwanted logic transients(noise) called glitches. A glitch is an unwanted transient in an otherwise steady state signal and may appear as either a logic 0 -1-0 (positive glitch) or as a logic 1-0-1 (negative) glitch as shown below. 1
2. 2. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com A glitch that occurs as a result of two or more state variable changes during a state-to state transition is called an output race glitch or simply ORG .So,an ORG may be regarded as an internally initiated function hazard. STATE DIAGRAMS : The State diagram models a state machine by using circles to represent each of the possible states and arrows to represent all of the possible transitions between the states. Let us consider the example below. The upper half of each circle indicates the name of the state. The lower half indicates the binary output associated with that state. In the case of the light bulb state machine, a zero is output while we are in the OFF state and a one is output while we are in the ON state. The arrows along with the input value say that when we are in state OFF and the switch input goes to a 1, move to state ON. When we are in state ON and the switch input goes to a 0, move to state OFF. Let's design a 3-bit up/down binary counter as a state machine. The block diagram of the counter is shown below. One of the inputs to this counter is a clock. In general many state machines have a clock. It is used to drive the system from one state to the next. To do this, it is connected to the clock input of the latches. When a pulse is received, the next state is stored in the latches where it becomes the current state. The other input to our system is direction. The direction signal is a binary input to indicate the system whether the stored value is to be incremented or decremented. 2
3. 3. Dr.Y.Narasimha Murthy Ph.D yayavaram@yahoo.com [ Normally when direction bit is 0 we will be decrementing and when direction bit is 1 we will be incrementing]. There is an additional important information that must be represented with a state diagram. When a system first powers up, it should be initialized to a reset state. We need to indicate on the diagram which state is defined as the initial state A 3-bit counter has an output that is a three-bit number. Every time a clock pulse occurs, the counter will change state to either increment or decrement the output depending on the value of direction. For example, if direction equals one, then each clock pulse will increment the output through the sequence 000, 001, 010, 011, 100, 101, 110, 111, 000, 001, etc. If direction equals zero, then the output will decrement once for each clock pulse, i.e., 000, 111, 110, 101, 100,011, 010, 001, 000, 111, 001, etc. The arrows going clockwise around the inside of the diagram represent the progression through the states at each clock pulse when direction equals 1. The arrows going counter clockwise around the outside of the diagram represent the progression through the states at each clock pulse when direction equals zero. Parity Checker: The parity checker is a simple logic circuit which has one input , and one output in addition to a clock input. This is a simple sequential circuit or FSM. When a sequence of 0‟s and 1‟s is applied to the X input, the output of the circuit should be (Z) = 1 if the total number of 1 inputs received is odd ; that is, the output should be 1 if the input parity is odd. Thus, if data which originally had odd parity is transmitted to the circuit, a final output of 3