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Arteris backgroundArteris background
• Arteris, Inc.Arteris, Inc. is ais a multinationalmultinational technologytechnology firm that develops the on-chipfirm that develops the on-chip
interconnect fabric technology used ininterconnect fabric technology used in System-on-Chip (SoC)System-on-Chip (SoC) semiconductorsemiconductor designsdesigns
for a variety of devices, particularly infor a variety of devices, particularly in mobilemobile andand consumerconsumer markets.markets.[1][1][2][2] TheThe
company specializes in the development and distribution ofcompany specializes in the development and distribution of Network-on-Chip (NoC)Network-on-Chip (NoC)
interconnectinterconnect Intellectual Property (IP)Intellectual Property (IP) solutions.solutions.[1][1][2][2][3][3] It is best known for itsIt is best known for its
flagship productflagship product, Arteris FlexNoC, which is used in more than 60 percent of mobile, Arteris FlexNoC, which is used in more than 60 percent of mobile
andand wirelesswireless SoC designs.SoC designs.[1][1][4][4]
• Arteris, Inc. is headquartered inArteris, Inc. is headquartered in Campbell, CaliforniaCampbell, California..[5][5] K. Charles Janac is theK. Charles Janac is the
company’s President andcompany’s President and CEOCEO..[6][6]
• In 2012, theIn 2012, the Silicon ValleySilicon Valley San Jose Business JournalSan Jose Business Journal ranked Arteris as the 4thranked Arteris as the 4th
fastest-growing private company in Silicon Valley.fastest-growing private company in Silicon Valley.[7][7] Arteris has also been in the Inc.Arteris has also been in the Inc.
500 list of America’s fastest growing companies for two years running.500 list of America’s fastest growing companies for two years running.[1][1][8][8]
• Arteris was founded in 2003 by Philippe Boucard and two other engineeringArteris was founded in 2003 by Philippe Boucard and two other engineering
executives who had worked together at T.Sqware, aexecutives who had worked together at T.Sqware, a startupstartup that was acquired bythat was acquired by
Globespan.Globespan.[9][9][10][10][11][11] Company executives wished to address problems with existingCompany executives wished to address problems with existing
monolithic bus and crossbar interconnect technologies, such as wire andmonolithic bus and crossbar interconnect technologies, such as wire and routingrouting
congestioncongestion, increased heat and power consumption, failed, increased heat and power consumption, failed timing closuretiming closure, and, and
increasedincreased die areadie area..[2][2][12][12][13][13][14][14] The firm’s leadership sought and receivedThe firm’s leadership sought and received
venture capitalventure capital totaling $44.1 million for the creation of its new technology fromtotaling $44.1 million for the creation of its new technology from
investorsinvestors, including, including ARM HoldingsARM Holdings, Crescendo Ventures, DoCoMo Capital,, Crescendo Ventures, DoCoMo Capital,
QualcommQualcomm,, SynopsysSynopsys, TVM Capital, and Ventech., TVM Capital, and Ventech.[12][12][15][15][16][16]
• By 2006, Arteris developed the first commercially available NoC IP product, calledBy 2006, Arteris developed the first commercially available NoC IP product, called
NoC Solution, followed in 2009 by a more advanced product, FlexNoC.[2][17][18] TheNoC Solution, followed in 2009 by a more advanced product, FlexNoC.[2][17][18] The
products used “packetization and a distributed network of small interconnectproducts used “packetization and a distributed network of small interconnect
elements to address congestion, timing, power and performance issues.”[2][19]elements to address congestion, timing, power and performance issues.”[2][19]
Arteris marketed FlexNoC as an improvement on traditional SoCs interconnectArteris marketed FlexNoC as an improvement on traditional SoCs interconnect](https://image.slidesharecdn.com/2047d6a9-a329-4390-b57a-395ce7b48597-150705025942-lva1-app6891/85/NoC-Modem-design_strategies_35A-3-320.jpg)
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Oblivious routing algorithms
ALGORITHM OUTLINES FEATURES REFERENCE S
Dimension order
XY
Pseudo adaptive XY
Surrounding XY
Turn model Valiant’s random
Source
Destination-tag
ALOAS
Topology adaptive
Probabilistic flood Directed
flood
Random walk
routing in one dimension at a
time
routing first in X and then in Y
dimension
partly adaptive XY
routing
partly adaptive XY
routing
some turns forbidden partly
stochastic deterministic, sender
determines the route
deterministic, routers determine
the route
deterministic, applica- tion of
source routing
reprogrammable routing tables
stochastic stochastic
stochastic
simple
simple, loads network deadlock-
and livelock- free
livelock-free, congestion avoidance
congestion avoidance
livelock-free
balances network’s load simple
routing
simple sending fast routing
suitable to dynamic networks
cheap, consumes a lot of resources
fault-tolerant, consumes a lot of
resources
fault-tolerant
[12]
[15]
[15] [9]
[20] [12]
[13, 35]
[12, 18, 28] [29, 35]
[23] [6, 7] [30] [30]
[30]](https://image.slidesharecdn.com/2047d6a9-a329-4390-b57a-395ce7b48597-150705025942-lva1-app6891/85/NoC-Modem-design_strategies_35A-7-320.jpg)
![8
Adaptive routing algorithms
ALGORITHM OUTLINES FEATURES REFERENCE S
Dimension order
XY
Pseudo adaptive XY
Surrounding XY
Turn model Valiant’s random
Source
Destination-tag
ALOAS
Topology adaptive
Probabilistic flood Directed
flood
Random walk
routing in one dimension at a
time
routing first in X and then in Y
dimension
partly adaptive XY
routing
partly adaptive XY
routing
some turns forbidden partly
stochastic deterministic, sender
determines the route
deterministic, routers determine
the route
deterministic, applica- tion of
source routing
reprogrammable routing tables
stochastic stochastic
stochastic
simple
simple, loads network deadlock-
and livelock- free
livelock-free, congestion
avoidance
congestion avoidance
livelock-free
balances network’s load simple
routing
simple sending fast routing
suitable to dynamic networks
cheap, consumes a lot of
resources
fault-tolerant, consumes a lot of
resources
fault-tolerant
[12]
[15]
[15] [9]
[20] [12]
[13, 35]
[12, 18, 28] [29, 35]
[23] [6, 7] [30] [30]
[30]](https://image.slidesharecdn.com/2047d6a9-a329-4390-b57a-395ce7b48597-150705025942-lva1-app6891/85/NoC-Modem-design_strategies_35A-8-320.jpg)
![9
Router architectures
ROUTER TOPOLOGY FLOW CTRL ALGORITHM SPECIAL REF.
Oblivious
VCR
Xpipes
Æthereal
Proteo
MANGO
SoCBUS
Arteris
STNoC
2-dimensional
Any
Mesh
Ring and subnets
Mesh
Mesh
User-defined
Spidergon
Wormhole
Wormhole
Wormhole
Wormhole
Wormhole
Store-and- forward
User-defined
Wormhole
Source routing
Source routing
Contention free source
routing
Destination-tag
Source routing
Destination-tag
User-defined
Source routing
Virtual channels
Well adaptable
Combined GT
and BE
Layered structure
GT and BE traffic
Circuit switching
Commercial
Commercial
[22]
[10]
[16]
[2] [8]
[34]
[5] [32]
Adaptive
DyAD
SPIN XGFT
Nostrum
Mesh
Fat tree
Fat tree
Mesh
Wormhole
Wormhole
Wormhole variant
Virtual cut-
through
XY, Odd-Even
Turn around
Turn around, source
routing
Hot-potato
Dynamically
deterministic and
adaptive
Fault-tolerant
No buffers
[19]
[1] [21]
[27]](https://image.slidesharecdn.com/2047d6a9-a329-4390-b57a-395ce7b48597-150705025942-lva1-app6891/85/NoC-Modem-design_strategies_35A-9-320.jpg)
NoC & Modem design_strategies_35A
- 1. 1111 The opportunities ofNoC &The opportunities of NoC & Modem design services fromModem design services from Arteris and Sonics patentArteris and Sonics patent strategiesstrategies By Joney ChenBy Joney Chen 2015-07-032015-07-03
- 2. 2 22 OUTLINEOUTLINE • ArtiesbackgroundArties background • FlexNoC function/feature design flowFlexNoC function/feature design flow • Arties PIP provider satisfy their customersArties PIP provider satisfy their customers • Trace/Analyze 3 tablesTrace/Analyze 3 tables • Arteris Patent set upArteris Patent set up • Modem design strategiesModem design strategies
- 3. 3 33 Arteris backgroundArterisbackground • Arteris, Inc.Arteris, Inc. is ais a multinationalmultinational technologytechnology firm that develops the on-chipfirm that develops the on-chip interconnect fabric technology used ininterconnect fabric technology used in System-on-Chip (SoC)System-on-Chip (SoC) semiconductorsemiconductor designsdesigns for a variety of devices, particularly infor a variety of devices, particularly in mobilemobile andand consumerconsumer markets.markets.[1][1][2][2] TheThe company specializes in the development and distribution ofcompany specializes in the development and distribution of Network-on-Chip (NoC)Network-on-Chip (NoC) interconnectinterconnect Intellectual Property (IP)Intellectual Property (IP) solutions.solutions.[1][1][2][2][3][3] It is best known for itsIt is best known for its flagship productflagship product, Arteris FlexNoC, which is used in more than 60 percent of mobile, Arteris FlexNoC, which is used in more than 60 percent of mobile andand wirelesswireless SoC designs.SoC designs.[1][1][4][4] • Arteris, Inc. is headquartered inArteris, Inc. is headquartered in Campbell, CaliforniaCampbell, California..[5][5] K. Charles Janac is theK. Charles Janac is the company’s President andcompany’s President and CEOCEO..[6][6] • In 2012, theIn 2012, the Silicon ValleySilicon Valley San Jose Business JournalSan Jose Business Journal ranked Arteris as the 4thranked Arteris as the 4th fastest-growing private company in Silicon Valley.fastest-growing private company in Silicon Valley.[7][7] Arteris has also been in the Inc.Arteris has also been in the Inc. 500 list of America’s fastest growing companies for two years running.500 list of America’s fastest growing companies for two years running.[1][1][8][8] • Arteris was founded in 2003 by Philippe Boucard and two other engineeringArteris was founded in 2003 by Philippe Boucard and two other engineering executives who had worked together at T.Sqware, aexecutives who had worked together at T.Sqware, a startupstartup that was acquired bythat was acquired by Globespan.Globespan.[9][9][10][10][11][11] Company executives wished to address problems with existingCompany executives wished to address problems with existing monolithic bus and crossbar interconnect technologies, such as wire andmonolithic bus and crossbar interconnect technologies, such as wire and routingrouting congestioncongestion, increased heat and power consumption, failed, increased heat and power consumption, failed timing closuretiming closure, and, and increasedincreased die areadie area..[2][2][12][12][13][13][14][14] The firm’s leadership sought and receivedThe firm’s leadership sought and received venture capitalventure capital totaling $44.1 million for the creation of its new technology fromtotaling $44.1 million for the creation of its new technology from investorsinvestors, including, including ARM HoldingsARM Holdings, Crescendo Ventures, DoCoMo Capital,, Crescendo Ventures, DoCoMo Capital, QualcommQualcomm,, SynopsysSynopsys, TVM Capital, and Ventech., TVM Capital, and Ventech.[12][12][15][15][16][16] • By 2006, Arteris developed the first commercially available NoC IP product, calledBy 2006, Arteris developed the first commercially available NoC IP product, called NoC Solution, followed in 2009 by a more advanced product, FlexNoC.[2][17][18] TheNoC Solution, followed in 2009 by a more advanced product, FlexNoC.[2][17][18] The products used “packetization and a distributed network of small interconnectproducts used “packetization and a distributed network of small interconnect elements to address congestion, timing, power and performance issues.”[2][19]elements to address congestion, timing, power and performance issues.”[2][19] Arteris marketed FlexNoC as an improvement on traditional SoCs interconnectArteris marketed FlexNoC as an improvement on traditional SoCs interconnect
- 4. 4 FlexNoC function/feature designflowFlexNoC function/feature design flow 1. User defined topology, flow control and algorithm. Maximum its flexibility. 2. Layout friendly FlexNoC IP, short time closure, synthesis and place & route , shorter TTM. 3. Eliminates trial-and-error timing closure with automated pipeline configuration. 4. Optimizes Quality-of-Results. 5. Separates the FlexNoC interconnect physical IP from the rest of the SoC.
- 5. 5 Arties PIP providersatisfy their customersArties PIP provider satisfy their customers TTM • Create, optimize and verify a SoC interconnect in one‐quarter the previous time. • Sophisticated end‐to‐end QoS is implementable and verifiable without unnecessary manual work. • Fast pinpointing and resolution of timing closure issues. • Quickly create derivative SoCs or respond to engineering changes in days rather than months. • Managers have confidence in SoC schedules due to reduced schedule risk. • Integrated and automated verification with VMM, OVM and UVM for highest IP quality.
- 6. 6 Trace/Analyze 3 tablesTrace/Analyze3 tables 1. Oblivious routing algorithms. 2. Adaptive routing algorithms. 3. Router architectures.
- 7. 7 Oblivious routing algorithms ALGORITHMOUTLINES FEATURES REFERENCE S Dimension order XY Pseudo adaptive XY Surrounding XY Turn model Valiant’s random Source Destination-tag ALOAS Topology adaptive Probabilistic flood Directed flood Random walk routing in one dimension at a time routing first in X and then in Y dimension partly adaptive XY routing partly adaptive XY routing some turns forbidden partly stochastic deterministic, sender determines the route deterministic, routers determine the route deterministic, applica- tion of source routing reprogrammable routing tables stochastic stochastic stochastic simple simple, loads network deadlock- and livelock- free livelock-free, congestion avoidance congestion avoidance livelock-free balances network’s load simple routing simple sending fast routing suitable to dynamic networks cheap, consumes a lot of resources fault-tolerant, consumes a lot of resources fault-tolerant [12] [15] [15] [9] [20] [12] [13, 35] [12, 18, 28] [29, 35] [23] [6, 7] [30] [30] [30]
- 8. 8 Adaptive routing algorithms ALGORITHMOUTLINES FEATURES REFERENCE S Dimension order XY Pseudo adaptive XY Surrounding XY Turn model Valiant’s random Source Destination-tag ALOAS Topology adaptive Probabilistic flood Directed flood Random walk routing in one dimension at a time routing first in X and then in Y dimension partly adaptive XY routing partly adaptive XY routing some turns forbidden partly stochastic deterministic, sender determines the route deterministic, routers determine the route deterministic, applica- tion of source routing reprogrammable routing tables stochastic stochastic stochastic simple simple, loads network deadlock- and livelock- free livelock-free, congestion avoidance congestion avoidance livelock-free balances network’s load simple routing simple sending fast routing suitable to dynamic networks cheap, consumes a lot of resources fault-tolerant, consumes a lot of resources fault-tolerant [12] [15] [15] [9] [20] [12] [13, 35] [12, 18, 28] [29, 35] [23] [6, 7] [30] [30] [30]
- 9. 9 Router architectures ROUTER TOPOLOGYFLOW CTRL ALGORITHM SPECIAL REF. Oblivious VCR Xpipes Æthereal Proteo MANGO SoCBUS Arteris STNoC 2-dimensional Any Mesh Ring and subnets Mesh Mesh User-defined Spidergon Wormhole Wormhole Wormhole Wormhole Wormhole Store-and- forward User-defined Wormhole Source routing Source routing Contention free source routing Destination-tag Source routing Destination-tag User-defined Source routing Virtual channels Well adaptable Combined GT and BE Layered structure GT and BE traffic Circuit switching Commercial Commercial [22] [10] [16] [2] [8] [34] [5] [32] Adaptive DyAD SPIN XGFT Nostrum Mesh Fat tree Fat tree Mesh Wormhole Wormhole Wormhole variant Virtual cut- through XY, Odd-Even Turn around Turn around, source routing Hot-potato Dynamically deterministic and adaptive Fault-tolerant No buffers [19] [1] [21] [27]
- 10. 10 Arteris Patent StrategiesArterisPatent Strategies • 1. Sonics sues Arteris for infringing patents Nov. 2011 • 2. Arteris counts Sonics patent infringing claims Jan. 2012 • 3. Qualcomm buys Arteris tech, team Oct. 2013 • 4. From EPO & USPTO web site analysis Arteris/Sonics patent set up.
- 11. 11 Modem designModem design strategiesstrategies •Matlab/Simulink math model operations. • Software/Firmware/Hardware analysis.
- 12.