The document provides an overview of network processors (NPs), detailing their definitions, applications, and hardware architectures. It emphasizes the importance of NPs in handling increasing data rates and dynamic protocols, highlighting their advantages over general-purpose processors and application-specific integrated circuits. Additionally, it discusses the functionality of various processor types, comparison between microprocessors and network processors, and the role of major companies like Amazon and Google in developing advanced processing technologies.

1. Supervised by
Prof. Dr. Dhuha Basheer
Prepared by
Ali Abdulwahab Yhya
Rian Sharafaldeen Yhya
Mahmood Mohammed Mahmood

2. 01
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OUTLINE
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04
05
06
Introduction to NP Systems
Relevant Applications
Design Issues and Challenges
Common Features in NPs
Hardware Architecture of NPs
Amazon and Google Processors

3. What are Network Processors
• Any device that executes programs to handle packets in a data
network.
• Generally some characteristics that enable efficient processing
of network headers in cells or packets.
• Is an integrated circuit that it is a software programmable device
designed specifically to process packet data at wire-speed as a
network architecture component inside a network application
domain.

4. Why Network Processors
 Current Situation
• Data rates are increasing
• Protocols are becoming more dynamic and sophisticated
• Protocols are being introduced more rapidly
 Processing Elements
GP(General-purpose Processor)
• Programmable, Not optimized for networking applications
ASIC(Application Specific Integrated Circuit)
• High processing capacity, long time to develop, Lack the flexibility
NP(Network Processor)
• achieve high processing performance
• programming flexibility
• Cheaper than GP

5. Applications
•Routers, software routers and switches
•Firewalls
•Intrusion detection devices
•Intrusion prevention devices
•Network monitoring systems
•Other applications:
Email
Files Transfer
IP Phone
Virtual Private Network (VPN)
E-commerce
Games

6. Network Processor In Router
A router is a special type of computer. It has the same basic
components as a standard desktop PC. It has a CPU, memory, a
system bus, and various input/output interfaces.
Just as computers need operating systems to run software
applications, routers need the Internet work Operating System
(IOS) software to run configuration files.

7. COMMON FEATURES IN NPS
 High Bandwidth and High Capacity Memories.
 Embedded and external SRAM and DRAM.
 Interface to a “host” control processor.
 Interface to coprocessors.
 High packet throughput speed.
 Low Packet latency.
 Low power and low Cost.
 Simple , standards-based software model.
 Flexible , high performance security support.

8. Organizing Processor Resources
 Design decisions:
• High-level organization
• ISA and micro architecture
• Memory and I/O integration
 Today’s commercial NPs:
• Chip multiprocessors
• Most are multithreaded
• Exploit little ILP (Cisco does)
• No cache
• Micro-programmed

9. NETWORK ELEMENTS ARE
USUALLY ARCHITECTED IN
TWO SEPARATED PLANES
 The control plane: is responsible
for signaling as well as other
control and management protocol
processing and implementation.
 The data plane: forwards the traffic based on decisions that the
control plane makes, according to information the control plane
collects [4,5].

10. Hardware Architecture (NP)

11. Hardware Architecture (NP)
• Lookup Engine
NP takes a packet field and performs a lookup in a table to return the relevant
table entry.
• Network Interface
where the data packets enter and exit the NP, these interfaces connect to another
devices of the line interface.
• Control Processing
The main function of the Network Processor is to process packet data at wire-speed.
• Multiple Programmable Processing Engines (PPE)
In the definition of the network processor it refers to the network processor being
software programmable.

12. Hardware Architecture (NP)
• Memory
Network Processors require memory to store program code, lookup tables, packet
data and queue information. There are two types:
 SRAM
Small and frequently accessed data.
Routing table, Queuing information, Packet pointer.
 DRAM
Large and rate accessed data.
Packet data.
• Data Manipulation
This is where the packet is modified in some way.

13. Processor VS Network processors
µ Proc
Microprocessor
General purpose
Cache based pipeline
Wide instruction set
Various mathematics
Multi-task
Network Processor
Focused on packets
Decision pipeline
Network instruction set
Fast binary decision
Real-time

14. ARM Processor

15. ARM processor
• An ARM processor: Is one of a family of CPUs based on
the RISC (Reduced Instruction Set Computer) architecture.
• ARM makes 32-bit and 64-bit RISC multi-core processors. RISC processors are
designed to perform a smaller number of types of computer instructions so that
they can operate at a higher speed, performing more Millions of Instructions Per
Second (MIPS).
• Because of their reduced instruction set, they require fewer transistors, which
enables a smaller die size for the Integrated Circuitry (IC) [3].

16. ARM processor
• ARM processors are extensively used in consumer electronic devices such as:
* Smartphones * Tablets
* Multimedia Players * Wearables

17. ARM processor features
• Smaller size.
• Reduced complexity.
• Lower power consumption.
• Mostly single-cycle execution.
• Enhanced power-saving design.
• 64 and 32-bit execution states for scalable high performance.
• Hardware Virtualization support [3].

18. Amazon AWS Processors

19. Amazon AWS Processors

20. Google Processors
Data centers that require the best CPU
performance, security features, and
scalability count on AMD EPYC™.

21. Google Processors

22. The Next Generation
Quantum Processors

23. REFERENCES
1. [NPT] W. H. Mangione-Smith, G. Memik Network Processor Technologies
2. [NPRD] Patrick Crowley, Raj Yavatkar An Introduction to Network Processor
Research & Design, HPCA-9 Tutorial
3. Reid, A. (2016, October). Trustworthy specifications of ARM® v8-A and v8-M
system level architecture. In 2016 Formal Methods in Computer-Aided Design
(FMCAD) (pp. 161-168). IEEE.
4. Khosravi, H., and Anderson, T., Requirements for Separation of IP Control and
Forwarding, RFC 3654, IETF, 2003.
5. Yang, L., Dantu, R., Anderson, T., and Gopal, R., Forwarding and Control Element
Separation (ForCES) Framework, RFC 3746, IETF, 2004.

24. THANK YOU
ANY QUESTIONS?