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Publications:
I am currently the author of 11 peer-reviewed journal and conference publications.
Enlisted are selected publications:

   1. D. Ghai, S. P. Mohanty, and E. Kougianos, “Design of Parasitic and Process-
      Variation Aware Nano-CMOS RF Circuits: A VCO Case Study”, in IEEE
      Transactions on Very Large Scale Integration Systems (TVLSI), in press
   2. D. Ghai, S. P. Mohanty, and E. Kougianos, “Unified P4 (Power-Performance-
      Process-Parasitic) Fast Optimization of a Nano-CMOS VCO”, in Proceedings
      of the 19th ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 303-
      308, 2009.
   3. D. Ghai, S. P. Mohanty, and E. Kougianos, “Variability-Aware Optimization of
      Nano-CMOS Active Pixel Sensors using Design and Analysis of Monte Carlo
      Experiments”, accepted in Proceedings of the 10th IEEE International
      Symposium on Quality Electronic Design (ISQED), 2009.
   4. D. Ghai, S. P. Mohanty, E. Kougianos, and P. Patra, “A PVT Aware Accurate
      Statistical Logic Library for High-K Metal-Gate Nano-CMOS”, in Proceedings
      of the 10th IEEE International Symposium on Quality Electronic Design
      (ISQED), pp. 47-54, 2009.
   5. D. Ghai, S. P. Mohanty, and E. Kougianos, “A Process and Supply Variation
      Tolerant Nano-CMOS Low Voltage, High Speed, A/D Converter for System-
      on-Chip”, in Proceedings of the 18th ACM/IEEE Great Lakes Symposium on
      VLSI (GLSVLSI), 2008, pp. 47-52.
   6. D. Ghai, S. P. Mohanty, and E. Kougianos, “A Dual Oxide CMOS Universal
      Voltage Converter for Power Management in Multi-V DD SoCs”, in Proceedings
      of the 9th IEEE International Symposium on Quality Electronic Design
      (ISQED), 2008, pp. 257-260.
   7. D. Ghai, S. P. Mohanty, and E. Kougianos, “Parasitic Aware Process Variation
      Tolerant Voltage Controlled Oscillator (VCO) Design”, in Proceedings of the
      9th IEEE International Symposium on Quality Electronic Design (ISQED),
      2008, pp. 330-333.
   8. S. P. Mohanty, E. Kougianos, D. Ghai, and P. Patra, “Interdependency Study of
      Process and Design Parameter Scaling for Power Optimization of Nano-CMOS
      Circuits under Process Variation”, in Proceedings of the 16th ACM/IEEE
      International Workshop on Logic and Synthesis (IWLS), pp. 207-213, 2007.

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My Publications

  • 1. Publications: I am currently the author of 11 peer-reviewed journal and conference publications. Enlisted are selected publications: 1. D. Ghai, S. P. Mohanty, and E. Kougianos, “Design of Parasitic and Process- Variation Aware Nano-CMOS RF Circuits: A VCO Case Study”, in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), in press 2. D. Ghai, S. P. Mohanty, and E. Kougianos, “Unified P4 (Power-Performance- Process-Parasitic) Fast Optimization of a Nano-CMOS VCO”, in Proceedings of the 19th ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 303- 308, 2009. 3. D. Ghai, S. P. Mohanty, and E. Kougianos, “Variability-Aware Optimization of Nano-CMOS Active Pixel Sensors using Design and Analysis of Monte Carlo Experiments”, accepted in Proceedings of the 10th IEEE International Symposium on Quality Electronic Design (ISQED), 2009. 4. D. Ghai, S. P. Mohanty, E. Kougianos, and P. Patra, “A PVT Aware Accurate Statistical Logic Library for High-K Metal-Gate Nano-CMOS”, in Proceedings of the 10th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 47-54, 2009. 5. D. Ghai, S. P. Mohanty, and E. Kougianos, “A Process and Supply Variation Tolerant Nano-CMOS Low Voltage, High Speed, A/D Converter for System- on-Chip”, in Proceedings of the 18th ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), 2008, pp. 47-52. 6. D. Ghai, S. P. Mohanty, and E. Kougianos, “A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-V DD SoCs”, in Proceedings of the 9th IEEE International Symposium on Quality Electronic Design (ISQED), 2008, pp. 257-260. 7. D. Ghai, S. P. Mohanty, and E. Kougianos, “Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design”, in Proceedings of the 9th IEEE International Symposium on Quality Electronic Design (ISQED), 2008, pp. 330-333. 8. S. P. Mohanty, E. Kougianos, D. Ghai, and P. Patra, “Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits under Process Variation”, in Proceedings of the 16th ACM/IEEE International Workshop on Logic and Synthesis (IWLS), pp. 207-213, 2007.