The document compares RISC and CISC architectures, highlighting RISC's fixed 32-bit instruction size and load-store design with a large register bank. In contrast, CISC features variable length instruction sets and larger but purpose-specific registers. Additionally, it discusses the differences in instruction decoding and execution efficiency between the two architectures.

2. RISC CISC
Fixed (32bit) instruction size with few
formats
Variable length instruction sets with many
formats
A load store architecture where
instructions that process data only on
registers and are separate from
instructions that access memory
Allowed values in memory to be used
as operands in data processing
instructions.
Fixed (32bit) instruction size with few
formats
Variable length instruction sets with many
formats
A large register bank of 32 bit registers, all
of which could be used for any purpose, to
allow load- store architecture to operate
efficiently
CISC register sets were getting larger, but
none was this large and most has different
registers for different purposes

3. RISC CISC
Hard-wired instruction decode logic Microcode ROM decode the instructions
Pipelined execution Overlap between consecutive instructions
Single cycle execution Take many clock cycles to complete a
single instruction

15. C source C libraries
asm
source
.aof
C compiler assembler
linker
Object
libraries
.aif
ARMsd
System
model
ARMulator
Developmen
t board
debu
g