This document describes the components and operation of the Intel 8085 microprocessor. It contains: - Details of the buses (data, address, control), registers (program counter, stack pointer, flags), arithmetic logic unit, and timing/control circuitry. - Explanations of the address bus width, data bus width, and bus multiplexing used to alternate between address and data on the lower order address lines. - Pin configurations and signals for clock input/output, address/data buses, and control signals like HOLD and HLDA used for direct memory access. - Timing diagrams showing the fetch-execute sequence where the program counter addresses memory to fetch instructions.

4.  Buses
 Registers
 ALU
 Flags
 Program Counter
 Stack Pointer
 Instruction registers and decoders
Timing and control circuitry

6. Busses
 Data Bus
 Address Bus
 Control Bus

7. Data Bus
8 bits wide (D0 D1…D7).So Bus Width is 8
“Bi-directional”.
Information flows both ways between the
microprocessor and memory or I/O.
The 8085 uses the data bus to transfer the
binary information.Word length is 8.
Word length = Bus Width
Control Bus
It must for Proper Operation
I/O single Control lines
Synchronize the operation between
microprocessor and external circuitry

8. Address Bus
16 bits wide (A0 A1…A15)
Therefore, the 8085 can access locations with numbers from
0 to 65,536. Or, the 8085 can access a total of 64K addresses.
“Unidirectional”.
Information flows out of the microprocessor and into the
memory or peripherals.
Divide into 2 part: A15 – A8 (upper) and
AD7 – AD0 (lower).
A15 – A8 : Unidirectional, known as ‘high order address’.
AD7 – AD0 : bidirectional and dual purpose (address and data
placed once at a time).
AD7 – AD0 also known as ‘low order address’.
To execute an instruction, at early stage AD7 – AD0 uses as
address bus and alternately as data bus for the next cycle.
The method to change from address bus to data bus known as
‘bus multiplexing’.

9. Registers
 Six 8 bit General
purpose Registers to
store the data
 16 Bit Registers pair
BC,DE,HL
H & L is used as data
pointer

10. ALU
 Heart of microprocessor
 arithmetic & logic operation. Such as ADD,OR etc.
Accumulator
8-bit register that is part of the ALU Used to store 8-bit data and
in performing 8-bit arithmetic and logical operations, and in
storing the results operations or they can be transferred to the
internal data bus for use elsewhere

11. Flags register
Sign Flag

13. AC-Auxiliary Carry
This flag is set when a carry is generated from bit D3
and passed to D4 . This flag is used only internally
for BCD operations.
P-Parity flag
After an ALU operation if the result has an
even no of 1’s the p-flag is set. Otherwise it
is cleared. So, the flag can be used to
indicate even parity.

14. PROGRAM COUNTER (PC)
STACK POINTER (SP)

15. Intel 8085 Pin Configuration

16.  8085 MPU has 3 pins that control or present the clock
signal.
 X1 and X2 pins determine the clock frequency.
 CLK OUT is a TTL square-wave output clock.
 The CLOCK OUT is one-half the crystal
frequency.
8085 Pinout

17.  8085 μp consists of 16 signal pins use as address
bus.
 Divide into 2 part: A15 – A8 (upper) and
AD7 – AD0 (lower).
 A15 – A8 : Unidirectional, known as ‘high order
address’.
 AD7 – AD0 : bidirectional and dual purpose
(address and data placed once at a time).
 AD7 – AD0 also known as ‘low order address’.
 To execute an instruction, at early stage AD7 –
AD0 uses as address bus and alternately as data
bus for the next cycle.
 The method to change from address bus to data
bus known as ‘bus multiplexing’.

18. Control and Status Signals.

19. Direct Memory Access (DMA)
 DMA is an IO technique where external IO device
requests the use of the MPU buses.
 Allows external IO devices to gain high speed access to
the memory.
 Example of IO devices that use DMA: disk memory system.
 HOLD and HLDA are used for DMA.
 If HOLD=1, 8085 will place it address, data and control
pins at their high-impedance.
 A DMA acknowledgement is signaled by HLDA=1.

20. 20
MPU Communication and Bus Timing
Figure 3: Moving data form memory to MPU using instruction MOV C, A
(code machine 4FH = 0100 1111)

21. 21
 The Fetch Execute Sequence :
1. The μp placed a 16 bit memory address from PC
(program counter) to address bus.
– Figure 4: at T1
– The high order address, 20H, is placed at A15 – A8.
– the low order address, 05H, is placed at AD7 - AD0 and
ALE is active high.
– Synchronously the IO/M is in active low condition to show it
is a memory operation.
2. At T2 the active low control signal, RD, is activated so as
to activate read operation; it is to indicate that the MPU
is in fetch mode operation.
MPU Communication and Bus
Timing

22. 22
Figure 4: 8085 timing diagram for Opcode fetch cycle for MOV C, A .
MPU Communication and Bus Timing