Conditional branches and loops in assembler rely on testing status flags in the status register (sreg) or individual bits in general purpose registers and I/O registers. The tutorial discusses different types of conditional branches including branches based on status flags set by compare instructions, branches to skip instructions if register bits are set or cleared, and examples using these branches to construct simple loops. It provides an introduction to conditional branching and looping for beginners in assembler programming.
I am Frank Allen. I am a Computer Architecture Assignment Expert at architectureassignmenthelp.com. I hold a Master's in Computer Architecture from, Ontario Tech University, Canada. I have been helping students with their assignments for the past 10 years. I solve assignments related to Computer Architecture.
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A new version of Firebird DBMS was released not so long ago. This release was one of the most significant in the project's history, as it marked substantial revision of the architecture, addition of multithreading support, and performance improvements. Such a significant update was a good occasion for us to scan Firebird one more time with PVS-Studio static code analyzer.
A new version of Firebird DBMS was released not so long ago. This release was one of the most significant in the project's history, as it marked substantial revision of the architecture, addition of multithreading support, and performance improvements. Such a significant update was a good occasion for us to scan Firebird one more time with PVS-Studio static code analyzer.
In this presentation we will cover Subroutines and Flag variables of arm architecture. And also Information About ARM Architecture registers Flag variables and subroutines.
Functions allow structuring the programs in segments of code to perform individual tasks. The typical case for creating a function is when one needs to perform the same action multiple times in a program.
Standardizing code fragments into functions has several advantages −
Functions help the programmer stay organized. Often this helps to conceptualize the program.
Functions codify one action in one place so that the function only has to be thought about and debugged once.
This also reduces chances for errors in modification, if the code needs to be changed.
Functions make the whole sketch smaller and more compact because sections of code are reused many times.
They make it easier to reuse code in other programs by making it modular, and using functions often makes the code more readable.
I am Frank Allen. I am a Computer Architecture Assignment Expert at architectureassignmenthelp.com. I hold a Master's in Computer Architecture from, Ontario Tech University, Canada. I have been helping students with their assignments for the past 10 years. I solve assignments related to Computer Architecture.
Visit architectureassignmenthelp.com or email info@architectureassignmenthelp.com. You can also call on +1 678 648 4277 for any assistance with Computer Architecture Assignments.
A new version of Firebird DBMS was released not so long ago. This release was one of the most significant in the project's history, as it marked substantial revision of the architecture, addition of multithreading support, and performance improvements. Such a significant update was a good occasion for us to scan Firebird one more time with PVS-Studio static code analyzer.
A new version of Firebird DBMS was released not so long ago. This release was one of the most significant in the project's history, as it marked substantial revision of the architecture, addition of multithreading support, and performance improvements. Such a significant update was a good occasion for us to scan Firebird one more time with PVS-Studio static code analyzer.
In this presentation we will cover Subroutines and Flag variables of arm architecture. And also Information About ARM Architecture registers Flag variables and subroutines.
Functions allow structuring the programs in segments of code to perform individual tasks. The typical case for creating a function is when one needs to perform the same action multiple times in a program.
Standardizing code fragments into functions has several advantages −
Functions help the programmer stay organized. Often this helps to conceptualize the program.
Functions codify one action in one place so that the function only has to be thought about and debugged once.
This also reduces chances for errors in modification, if the code needs to be changed.
Functions make the whole sketch smaller and more compact because sections of code are reused many times.
They make it easier to reuse code in other programs by making it modular, and using functions often makes the code more readable.
Water billing management system project report.pdfKamal Acharya
Our project entitled “Water Billing Management System” aims is to generate Water bill with all the charges and penalty. Manual system that is employed is extremely laborious and quite inadequate. It only makes the process more difficult and hard.
The aim of our project is to develop a system that is meant to partially computerize the work performed in the Water Board like generating monthly Water bill, record of consuming unit of water, store record of the customer and previous unpaid record.
We used HTML/PHP as front end and MYSQL as back end for developing our project. HTML is primarily a visual design environment. We can create a android application by designing the form and that make up the user interface. Adding android application code to the form and the objects such as buttons and text boxes on them and adding any required support code in additional modular.
MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software. It is a stable ,reliable and the powerful solution with the advanced features and advantages which are as follows: Data Security.MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
The Internet of Things (IoT) is a revolutionary concept that connects everyday objects and devices to the internet, enabling them to communicate, collect, and exchange data. Imagine a world where your refrigerator notifies you when you’re running low on groceries, or streetlights adjust their brightness based on traffic patterns – that’s the power of IoT. In essence, IoT transforms ordinary objects into smart, interconnected devices, creating a network of endless possibilities.
Here is a blog on the role of electrical and electronics engineers in IOT. Let's dig in!!!!
For more such content visit: https://nttftrg.com/
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
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Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...
Microcontroladores: Tutorial de lenguaje ensamblador AVR: ramas y bucles condicionales
1. www.avrbeginners.net
Assembler Tutorial
Conditional Branches and Loops
Author: Christoph Redecker
Version: 1.0.2
Introduction to AVRs
Registers and Memories
Port I/O
Jumps, Calls and the Stack
Conditional Branches and Loops
Interrupts
Accessing C Structs in Assembler
This tutorial is licensed under a Creative Commons Attribution–NonCommercial–
NoDerivs 3.0 Unported License:
http://creativecommons.org/licenses/by-nc-nd/3.0/.
Permissions beyond the scope of this license may be available at
http://www.avrbeginners.net.
2. 1
Conditional branches and loops are closely connected
in assembler. Understanding conditional branches is one key
to understanding loops. Both come in a variety of ways, and
some of the different branch and loop types will be discussed
in this tutorial, including the loops known from the C program-
ming language. Bare asm code is provided that can be used to
construct simple for{;;}– or while()–loops.
No in–depth knowledge of C or assembler is required to
understand this tutorial. It is targeted at beginners and attempts
have been made to point out common pitfalls caused by the
AVR instruction set or architecture. Some technical aspects are
extremely simplified.
The choice of AVR registers in the examples is done in such In short: Register numbers should be
interpreted as “this or higher”.
a way that a register with the minimum of required features is
used. If the ldi instruction is used, it is used with one of the
registers r16 to r23. Those below that range don’t support ldi,
those above can be used for register pair operations like adiw.
Conditional branches
As the name implies, a conditional branch relies on some condi-
tion. From the instruction set summary, three main condition
categories can be identified:
Branches that test flags in the status register The status register (sreg)
contains information about the result of the last operation
— if that result actually set any bit (a flag) in sreg. If that
is the case is specified in the instruction set summary (and
manual). The program can branch if any one flag in sreg is
set or cleared.
Branches that test bits in general purpose registers The general pur-
pose registers r0 to r31 can be tested for a specific bit being
set or cleared, and the program can skip the next instruction
if such a condition is true.
Branches that test bits in I/O registers Similar to the usage of gen-
eral purpose registers, the state of bits I/O registers can also
be used for skipping an instruction.
Note that the bit–tests in registers (gen-
eral purpose and I/O) can not be used
to branch, but merely to skip an instruc-
tion!
Branches that test flags in the status register
The first category, flags in sreg, is the largest. A great number of
instructions leave information in sreg, and it is worth knowing
what this information can be. The different branch instructions
operate on this information, and the instruction set manual
provides a table that summarises the branch instructions and
3. 2
what the relevant flags are. To the unenlightened, this table is
no help; all others don’t need it because they know what the
status bits mean, and what conditional branch has to be used
in a particular situation.
Let’s start with a short example:
ldi r16, 5 Example with
cp
SREG:Z
breq
ldi r17, 5
cp r16, r17
breq equal
. . . // not executed
equal:
. . . // executed r16 = r17?
.
.
.
1 . . .
0
.
.
.
Figure 1: Effect of cp and breq
In the above code, two registers (r16 and r17) are loaded with
the same value (5) and are compared with each other, using
cp. The following branch (breq, branch if equal) branches to the
code that follows the label equal. If the register did not have
equal values, the branch instruction would not branch, and the
code following branch instruction would be executed.
So what is going on in sreg? When cp is used to compare
two registers, the core is basically subtracting them from each
other. If they are equal, the result is zero and the Zero Flag
(Z) in sreg is set. The following breq tests this flag and, if
it is set, branches. In fact, substituting cp r16,r17 with sub
r16,r17 would result in the same behavior for the branch, but
the result of the subtraction would be stored in r16. There is
a complementary instruction, brne (branch if not equal), which
branches when the Z flag is cleared.
r16 6= r17?
.
.
.
1 . . .
0
.
.
.
Figure 2: Effect of cp and brlo interact.
There are more flags than just Z in sreg, there are more
branch instructions that operate on them, and even more in-
structions that set or clear one or more flags — certainly too
many to list all possibilities here, and that indeed wouldn’t help
much. Instead, some examples are shown here that demonstrate
the usage of flags and branches.
Usage of the simple compare instruction is now extended by
just altering the values loaded in the two registers, but different
branches are used. First, the two unsigned tests brlo (branch if
lower) and brsh (branch if same or higher):
ldi r16, 5 cp
SREG:C
brlo
ldi r17, 7
cp r16, r17
brlo lower // branch if r16 < r17
. . . // not executed
lower:
. . . // executed
4. 3
In this case, cp sets the Carry Flag (C) flag in sreg. From the
instruction set manual, cp section: “C: Set if the absolute value
of the contents of Rr is larger than the absolute value of Rd;
cleared otherwise” (in our case r16 is Rd and r17 is Rr). The Operand names like Rd and Rr are de-
fined in the Instruction Set Manual.
branch instruction brlo tests C and, if it is set, branches.
The second “unsigned branch”, brsh, works just like brlo,
but branches if the carry flag is cleared:
ldi r16, 5 cp
SREG:C
brsh
ldi r17, 7
cp r16, r17
brsh sameOrHigher // branch if r16 >= r17
. . . // executed
sameOrHigher:
. . . // not executed
If r16 had been loaded with 7 or a higher number, cp would
have left the carry flag cleared and brsh would have branched.
The carry flag is also useful in arithmetic operations, for ex-
ample when an overflow must be detected (see the instruction
manual section on add), or for shifting a bit out of one register
and shifting it into another (see lsl, rol and similar instruc-
tions).
The two unsigned branches have the signed equivalents brlt
(branch if less than) and brge (branch if greater or equal). The sign
of a value is stored in the MSB, which is bit 7 for 8–bit values.
The core does not know how to interpret the values stored in
the registers, so the person writing the code is responsible for
telling the core if a value has to be interpreted as a signed value.
Not doing so can lead to an error:
ldi r16, -2 // stored as 254 Example of an error with
signed values
cp
SREG:C
brsh
ldi r17, 7
cp r16, r17
brsh sameOrHigher // branch if r16 >= r17 (unsigned)
. . . // executed this should not be executed!
sameOrHigher:
. . . not executed this should be executed instead!
The MSB of a value is set if it is negative, so if it is interpreted
as an unsigned number, it is treated like a number that is higher
than 128. This results in the erroneous behavior of the above
code, which misinterprets a negative number as being higher
than 128, and not lower than 7. Obviously, the carry flag is not
made for signed tests.
The Sign Flag (S) is used for signed tests. It is set when the
result of an operation was negative or a two’s complement over-
flow occured (that is an exclusive or). brlt and brge examine
just this flag, and branch appropriately:
5. 4
ldi r16, -2 signed values
cp
SREG:S
brlt
ldi r17, 7
cp r16, r17
brlt lessThan // branch if r16 < r17
. . .
lessThan:
. . . // executed
The usage of brge is equal to that of brsh (see above), the only
difference is that it interprets signed numbers correctly:
ldi r16, 7
signed values
cp
SREG:S
brge
ldi r17, -2
cp r16, r17
brge greaterOrEqual // branch if r16 >= r17
. . . // not executed
greaterOrEqual:
. . . // executed
cpse
r16 = r17?
.
.
.
0
skip this if equal
.
.
.
1
Figure 3: Flowchart for cpse
A special branching instruction is cpse (compare, skip if equal).
It is a comparison and a branch in one: two registers are com-
pared and, if they were equal, the next instruction is skipped
(this works for 1– and 2–word instructions). At first glance, this
seems a bit limiting, but see:
ldi r16, 1
ldi r17, 1
cpse r16, r17
rcall somethingBig // executed, because r16 = r17
. . . // executed even if r16 <> r17
Note that cpse does not set any sreg flags, unlike cp. Strictly
spoken, it doesn’t belong to the category of sreg flag branches,
but it is related to cp and it doesn’t fit into any of the other
categories either.
Branches that test bits in general purpose registers
General purpose registers can be used to store bitfields. If that
is the case, it might be useful to branch if a specific bit in the
register is set or cleared. Single bits can be interesting in other
situations as well, such as when the sign of a register’s value
needs to be known.
Two branching instructions can be used for single bits in
general purpose registers. These are sbrc (skip if bit in register is
cleared) and sbrs (skip if bit in register is set):
ldi r16, 0b10110000 sbrc
sbrs
srbc r16,7
rcall BitSevenIsSet // executed
6. 5
sbrc r16,6
rcall BitSixIsSet // not executed
sbrs r16,5
rcall BitFiveIsCleared // not executed
. . . // normal execution from here
The two instructions can be used for any general purpose regis-
ter from r0 to r31.
Branches that test bits in I/O registers
Using bits in I/O registers works just like using bits in general
purpose registers. This is handy if, for example, the state of
an input needs to be known or while waiting for an internal
peripheral to complete a data transfer (UART, TWI, . . . ).
Again, there are two branching instructions for these pur-
poses, sbic (skip if bit in I/O register is cleared) and sbis (skip if
bit in register is set):
sbi PORTA,0 sbic
sbis
sbic PORTA,0
rcall PortABitIsSet // executed
sbis PORTA,0
rcall PortABitIsSet // not executed
. . . // normal execution from here
The usage of sbic and sbis is limited to the lower 32 I/O
registers. Testing single bits in the extended I/O space must be
done with multiple instructions, for example: sbrc
extended I/O space
lds r0, TWSR
sbrc r0, TWIE
rcall TwiInt // executed if TWI interrupt flag is set
. . . // normal execution from here
However, if I/O flags are tested in this way, special care should This is more of an interrupt handling
issue and not discussed in detail here.
be taken not to interfere with interrupts service routines, which
could alter the state of the tested flag before it is handled by
other code.
The section about branches ends here. It’s time for loops, and
more branch instructions and sreg flags will be used along the
way.
Loops
Loops are code structures which can (but don’t have to) repeat
the same piece of code multiple times. Variables can be altered
before, during, or after each loop iteration. They need initiali-
sation. They might or might not be used by the loop code. All
these differences are important.
7. 6
Endless loop
The simplest of all loops is the endless loop. An AVR executes
instructions while it is not in any sleep mode, even if does not
have anything to accomplish. Ending a program must therefore
be done with an endless loop:
. . .
end:
rjmp end
This loop doesn’t contain any branch instruction, but most loops
that actually do something rely on them.
An endless loop is also often used for the main part of an
application; it then contains the application body which is
executed over and over. The application can be initialised and
also decide to perform some kind of shutdown:
.org 0 // the cpu jumps to here after reset The cpu might also be config-
ured to jump to the boot reset
vector!
. . . // initialisation code, executed once
main:
. . . // body, might eventually jump to shutdown
rjmp main
shutdown:
. . . // shutdown code, executed once
end:
rjmp end
The loop body can contain code that deliberately jumps out of
the loop, breaking it. The break statement in C does just that. break
while–loop
It is time to add a condition to the loop. The while–loop executes
a code block as long as some condition is true. This condition is
tested before the body code is executed. The following example
waits until the AVR’s internal EEPROM is ready for writing:
while: while–loop
sbic
sbic EECR, EEPE
breq eepromIsReady
rjmp while
eeIsReady:
. . . // this code could write to the EEPROM
Of course, it is possible to use a subroutine that performs a test,
and then returns the result in the status register’s T flag:
while: while–loop
SREG:T
brts
sbic
rcall testEe
brts eepromIsReady
8. 7
rjmp while
eeIsReady:
. . . // this code could write to the EEPROM
testEe:
clt // clear T flag
sbic EECR, EEPE
set // set T flag if EEPROM is ready
ret // and return
Using a subroutine instead of inline code is beneficial when
the subroutine is also used in other parts of code, outside the
while condition. Also, the subroutine shown here is very small
and simple, but overly complex compared to the code in the
previous example. In a practical application, replacing a one–
liner by a subroutine is a waste of both cpu time and program
memory.
do. . . while–loop
Constructing a do . . . while–loop from the while–loop is straight
forward. In the following code, the subroutine isLcdReady is
assumed to query the state of an LCD. If that LCD is ready for
new commands, isLcdReady sets the carry flag and returns. If
the LCD is not ready, the carry flag is cleared:
do: do . . . while–loop
breq
. . . // possibly some more body code
rcall isLcdReady // check if the LCD is ready
breq do
. . . // send a command to the LCD
Note that the T flag could also be used instead of the carry flag
— it depends on the needs of the code that surrounds the loop.
for–loop
For–loops can be used for simple counting, for indexing arrays,
iterating over lists and other things. There are many ways to
implement such a loop, but in simple cases they rely on a loop
variable and
• the initialisation of the loop variable,
• a condition that must be true for an iteration to be executed,
• the body code and
• a counting expression.
The following loop executes the body code ten times:
9. 8
ldi r16, 10 for–loop
dec
brne
for:
. . . // body code
dec r16
brne for
. . . // normal execution from here
Special attention must be paid to the registers that are used
by the body code. If r16 is altered, this may lead to errors,
but can also be desired in some cases (for adding an intera-
tion, for example). If the body code is large or confusing, the
loop variable can be “protected” by pushing it onto the stack
before, and popping it from the stack after the body code is
executed (example follows below). However, the above code is
not equivalent to
for(i = 10; i > 0; i--)
// body code
In C, the loop condition must be true before the body code is
executed. A small change in the assembler code makes them
equivalent (in this example the loop variable is also protected
by storing it on the stack):
ldi r16, 10 for–loop (C equivalent)
dec
breq
save and restore (on the stack)
clz // zero flag is not cleared by ldi!
for:
breq end
push r16 // save
. . . // body code
pop r16 // restore
dec r16
rjmp for
end:
. . . // normal execution from here
Unfortunately, this is more complicated than the variant above. Imitating C in assembler is not always a
good idea. Not doing so can quite often
make life easier.
It’s also possible to increment the loop variable in every
iteration. If the loop variable’s value is not important (when the
task is only to have a specific number of iterations), it can start
with a negative value and roll over to zero. The branch at the
end of the loop can then test for zero:
ldi r16, -10 for–loop
negative initialisation value
inc
brne
for:
. . . // body code
inc r16
brne for
. . . // normal execution from here
10. 9
If the value is important, the initialisation value must make
sense:
ldi r16, 0 // or use clr or a different value for–loop
inc
cpi
brne
for:
. . . // body code
inc r16
cpi r16, 10
brne for
. . . // normal execution from here
This is almost the same as the first down–counting example,
but uses an additional cpi in the loop and therefore is slower.
On the other hand, it is now possible to initialise it with any
desired value and to alter the final value as required, or to use
it for special purposes in the loop body.
There are many many more ways to implement a loop, but
these examples should get you started.