International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
AN EFFICIENT M-ARY QIM DATA HIDING ALGORITHM FOR THE APPLICATION TO IMAGE ERR...IJNSA Journal
Methods like edge directed interpolation and projection onto convex sets (POCS) that are widely used for image error concealment to produce better image quality are complex in nature and also time consuming. Moreover, those methods are not suitable for real time error concealment where the decoder may not have sufficient computation power or done in online. In this paper, we propose a data-hiding scheme for error concealment of digital image. Edge direction information of a block is extracted in the encoder and is embedded imperceptibly into the host media using quantization index modulation (QIM), thus reduces work load of the decoder. The system performance in term of fidelity and computational load is improved using M-ary data modulation based on near-orthogonal QIM. The decoder extracts the embedded
features (edge information) and those features are then used for recovery of lost data. Experimental results duly support the effectiveness of the proposed scheme.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Efficient video compression using EZWTIJERA Editor
In this article, wavelet based lossy video compression algorithm is presented. The motion estimation and compensation, being an important part in the compression, is based on segment movements. The proposed work is based on wavelet transform algorithm Embedded Zeroed WaveletTransform (EZWT). Based on the results of peak signal to noise ratio (PSNR), mean squared error (MSE), different videos are analyzed. Maintaining the PSNR to acceptable limits the proposed EZWT algorithm achieves very good compression ratios making the technique more efficient than the 2-Discrete Cosine Transform (DCT) in the H.264/AVC codec. The method is being suitable for low bit rate video showing highest compression ratio and very good PSNR of more than 30dB.
Analysis of the Iriscode Bioencoding SchemeCSCJournals
Cancelable biometrics is a technique used to enhance security and user privacy. These schemes are employed to generate multiple revocable data from the original biometric template. In this paper, the security of binary template transformations is evaluated, through a new transformation for iris templates, called bioencoding scheme. This transformation and its security is analyzed, using Boolean functions and non linear Boolean systems. A general discussion on binary template transformations is finally proposed.
Review and comparison of tasks scheduling in cloud computingijfcstjournal
Recently, there has been a dramatic increase in the popularity of cloud computing systems that rent
computing resources on-demand, bill on a pay-as-you-go basis, and multiplex many users on the same
physical infrastructure. It is a virtual pool of resources which are provided to users via Internet. It gives
users virtually unlimited pay-per-use computing resources without the burden of managing the underlying
infrastructure. One of the goals is to use the resources efficiently and gain maximum profit. Scheduling is a
critical problem in Cloud computing, because a cloud provider has to serve many users in Cloud
computing system. So scheduling is the major issue in establishing Cloud computing systems. The
scheduling algorithms should order the jobs in a way where balance between improving the performance
and quality of service and at the same time maintaining the efficiency and fairness among the jobs. This
paper introduces and explores some of the methods provided for in cloud computing has been scheduled.
Finally the waiting time and time to implement some of the proposed algorithm is evaluated
AN EFFICIENT M-ARY QIM DATA HIDING ALGORITHM FOR THE APPLICATION TO IMAGE ERR...IJNSA Journal
Methods like edge directed interpolation and projection onto convex sets (POCS) that are widely used for image error concealment to produce better image quality are complex in nature and also time consuming. Moreover, those methods are not suitable for real time error concealment where the decoder may not have sufficient computation power or done in online. In this paper, we propose a data-hiding scheme for error concealment of digital image. Edge direction information of a block is extracted in the encoder and is embedded imperceptibly into the host media using quantization index modulation (QIM), thus reduces work load of the decoder. The system performance in term of fidelity and computational load is improved using M-ary data modulation based on near-orthogonal QIM. The decoder extracts the embedded
features (edge information) and those features are then used for recovery of lost data. Experimental results duly support the effectiveness of the proposed scheme.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Efficient video compression using EZWTIJERA Editor
In this article, wavelet based lossy video compression algorithm is presented. The motion estimation and compensation, being an important part in the compression, is based on segment movements. The proposed work is based on wavelet transform algorithm Embedded Zeroed WaveletTransform (EZWT). Based on the results of peak signal to noise ratio (PSNR), mean squared error (MSE), different videos are analyzed. Maintaining the PSNR to acceptable limits the proposed EZWT algorithm achieves very good compression ratios making the technique more efficient than the 2-Discrete Cosine Transform (DCT) in the H.264/AVC codec. The method is being suitable for low bit rate video showing highest compression ratio and very good PSNR of more than 30dB.
Analysis of the Iriscode Bioencoding SchemeCSCJournals
Cancelable biometrics is a technique used to enhance security and user privacy. These schemes are employed to generate multiple revocable data from the original biometric template. In this paper, the security of binary template transformations is evaluated, through a new transformation for iris templates, called bioencoding scheme. This transformation and its security is analyzed, using Boolean functions and non linear Boolean systems. A general discussion on binary template transformations is finally proposed.
Review and comparison of tasks scheduling in cloud computingijfcstjournal
Recently, there has been a dramatic increase in the popularity of cloud computing systems that rent
computing resources on-demand, bill on a pay-as-you-go basis, and multiplex many users on the same
physical infrastructure. It is a virtual pool of resources which are provided to users via Internet. It gives
users virtually unlimited pay-per-use computing resources without the burden of managing the underlying
infrastructure. One of the goals is to use the resources efficiently and gain maximum profit. Scheduling is a
critical problem in Cloud computing, because a cloud provider has to serve many users in Cloud
computing system. So scheduling is the major issue in establishing Cloud computing systems. The
scheduling algorithms should order the jobs in a way where balance between improving the performance
and quality of service and at the same time maintaining the efficiency and fairness among the jobs. This
paper introduces and explores some of the methods provided for in cloud computing has been scheduled.
Finally the waiting time and time to implement some of the proposed algorithm is evaluated
Segmentation and recognition of handwritten digit numeral string using a mult...ijfcstjournal
In this paper, the use of Multi-Layer Perceptron (MLP) Neural Network model is proposed for recognizing
unconstrained offline handwritten Numeral strings. The Numeral strings are segmented and isolated
numerals are obtained using a connected component labeling (CCL) algorithm approach. The structural
part of the models has been modeled using a Multilayer Perceptron Neural Network. This paper also
presents a new technique to remove slope and slant from handwritten numeral string and to normalize the
size of text images and classify with supervised learning methods. Experimental results on a database of
102 numeral string patterns written by 3 different people show that a recognition rate of 99.7% is obtained
on independent digits contained in the numeral string of digits includes both the skewed and slant data.
SECURE OMP BASED PATTERN RECOGNITION THAT SUPPORTS IMAGE COMPRESSIONsipij
In this paper, we propose a secure Orthogonal Matching Pursuit (OMP) based pattern recognition scheme that well supports image compression. The secure OMP is a sparse coding algorithm that chooses atoms sequentially and calculates sparse coefficients from encrypted images. The encryption is carried out by using a random unitary transform. The proposed scheme offers two prominent features. 1) It is capable of
pattern recognition that works in the encrypted image domain. Even if data leaks, privacy can be maintained because data remains encrypted. 2) It realizes Encryption-then-Compression (EtC) systems, where image encryption is conducted prior to compression. The pattern recognition can be carried out using a
few sparse coefficients. On the basis of the pattern recognition results, the scheme can compress selected images with high quality by estimating a sufficient number of sparse coefficients. We use the INRIA dataset to demonstrate its performance in detecting humans in images. The proposal is shown to realize human detection with encrypted images and efficiently compress the images selected in the image recognition stage.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Software projects mostly exceeds budget, delivered late and does not meet with the customer’s satisfaction for years. In the past, many traditional development models like waterfall, spiral, iterative, and prototyping methods are used to build the software systems. In recent years, agile models are widely used in developing the software products. The major reasons are – simplicity, incorporating the requirement changes at any time, light-weight approach and delivering the working product early and in short duration. Whatever the development model used, it still remains a challenge for software engineer’s to accurately estimate the size, effort and the time required for developing the software system. This survey focuses on the existing estimation models used in traditional as well in agile software development.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Selection of intra prediction modes for intra frame coding in advanced video ...eSAT Journals
Abstract This paper proposes selection of Intra prediction modes for Intra frame coding in Advanced Video Coding Standard using Matlab. The proposed algorithm selects prediction modes for intra frame coding. There are nine prediction modes are there to predict the intra frame in AVC using Intra prediction,but all the prediction modes are not required for all the applications. Intra prediction is the first process of advanced video coding standard. It predicts a macro block by referring to its previous macro blocks to reduce spatial redundancy,appling all the prediction modes to predict intra frame it leads to more computational complexity is increased at the encoder of AVC. In the proposed algoriyhm, applied all the prediction modes(0-8) for prediction of intra frame but only few modes such as mode0, mode1, mode2,mode4,mode6 gives good PSNR, high comprssion ratio and low bit rate. Out of these modes mode2 gives good PSNR, compression ratio and redced bit rate, mode5, mode7 and mode8 gives lower PSNR, low compression ratio and increased bitrate compared to mode0,mode1, mode2, mode4 and mode6. The simulation results are presented using Matlab. The PSNR , compressed ratio and bit rate achived for different quantization parameters of mother daughter frames , foreman frames was presented. Keywords: AVC, PSNR, CAVLC, Macroblock, Prediction modes.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Image type water meter character recognition based on embedded dspcsandit
In the paper, we combined DSP processor with image processing algorithm and studied the
method of water meter character recognition. We collected water meter image through camera
at a fixed angle, and the projection method is used to recognize those digital images. The
experiment results show that the method can recognize the meter characters accurately and
artificial meter reading is replaced by automatic digital recognition, which improves working
efficiency.
An Approach for Iris Recognition Based On Singular Value Decomposition and Hi...paperpublications3
Abstract: This paper presents a new approach using Hidden Markov Model as classifier and Singular Values Decomposition (SVD) coefficients as features for iris recognition. As iris is a complex multi-dimensional structure and needs good computing techniques for recognition and it is an integral part of biometrics. Features extracted from a iris are processed and compared with similar irises which exist in database. The recognition of human irises is carried out by comparing characteristics of the iris to those of known individuals. Here seven state Hidden Markov Model (HMM)-based iris recognition system is proposed .A small number of quantized Singular Value Decomposition (SVD) coefficients as features describing blocks of iris images. SVD is a method for transforming correlated variables into a set of uncorrelated ones that better expose the various relationships among the original data item. This makes the system very fast. The proposed approach has been examined on CASIA database. The results show that the proposed method is the fastest one, having good accuracy.
Improving of Fingerprint Segmentation Images Based on K-MEANS and DBSCAN Clus...IJECEIAES
Nowadays, the fingerprint identification system is the most exploited sector of biometric. Fingerprint image segmentation is considered one of its first processing stage. Thus, this stage affects typically the feature extraction and matching process which leads to fingerprint recognition system with high accuracy. In this paper, three major steps are proposed. First, Soble and TopHat filtering method have been used to improve the quality of the fingerprint images. Then, for each local block in fingerprint image, an accurate separation of the foreground and background region is obtained by K-means clustering for combining 5-dimensional characteristics vector (variance, difference of mean, gradient coherence, ridge direction and energy spectrum). Additionally, in our approach, the local variance thresholding is used to reduce computing time for segmentation. Finally, we are combined to our system DBSCAN clustering which has been performed in order to overcome the drawbacks of K-means classification in fingerprint images segmentation. The proposed algorithm is tested on four different databases. Experimental results demonstrate that our approach is significantly efficacy against some recently published techniques in terms of separation between the ridge and non-ridge region.
Face Recognition Based Intelligent Door Control Systemijtsrd
This paper presents the intelligent door control system based on face detection and recognition. This system can avoid the need to control by persons with the use of keys, security cards, password or pattern to open the door. The main objective is to develop a simple and fast recognition system for personal identification and face recognition to provide the security system. Face is a complex multidimensional structure and needs good computing techniques for recognition. The system is composed of two main parts face recognition and automatic door access control. It needs to detect the face before recognizing the face of the person. In face detection step, Viola Jones face detection algorithm is applied to detect the human face. Face recognition is implemented by using the Principal Component Analysis PCA and Neural Network. Image processing toolbox which is in MATLAB 2013a is used for the recognition process in this research. The PIC microcontroller is used to automatic door access control system by programming MikroC language. The door is opened automatically for the known person according to the result of verification in the MATLAB. On the other hand, the door remains closed for the unknown person. San San Naing | Thiri Oo Kywe | Ni Ni San Hlaing ""Face Recognition Based Intelligent Door Control System"" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-4 , June 2019, URL: https://www.ijtsrd.com/papers/ijtsrd23893.pdf
Paper URL: https://www.ijtsrd.com/engineering/electrical-engineering/23893/face-recognition-based-intelligent-door-control-system/san-san-naing
Segmentation and recognition of handwritten digit numeral string using a mult...ijfcstjournal
In this paper, the use of Multi-Layer Perceptron (MLP) Neural Network model is proposed for recognizing
unconstrained offline handwritten Numeral strings. The Numeral strings are segmented and isolated
numerals are obtained using a connected component labeling (CCL) algorithm approach. The structural
part of the models has been modeled using a Multilayer Perceptron Neural Network. This paper also
presents a new technique to remove slope and slant from handwritten numeral string and to normalize the
size of text images and classify with supervised learning methods. Experimental results on a database of
102 numeral string patterns written by 3 different people show that a recognition rate of 99.7% is obtained
on independent digits contained in the numeral string of digits includes both the skewed and slant data.
SECURE OMP BASED PATTERN RECOGNITION THAT SUPPORTS IMAGE COMPRESSIONsipij
In this paper, we propose a secure Orthogonal Matching Pursuit (OMP) based pattern recognition scheme that well supports image compression. The secure OMP is a sparse coding algorithm that chooses atoms sequentially and calculates sparse coefficients from encrypted images. The encryption is carried out by using a random unitary transform. The proposed scheme offers two prominent features. 1) It is capable of
pattern recognition that works in the encrypted image domain. Even if data leaks, privacy can be maintained because data remains encrypted. 2) It realizes Encryption-then-Compression (EtC) systems, where image encryption is conducted prior to compression. The pattern recognition can be carried out using a
few sparse coefficients. On the basis of the pattern recognition results, the scheme can compress selected images with high quality by estimating a sufficient number of sparse coefficients. We use the INRIA dataset to demonstrate its performance in detecting humans in images. The proposal is shown to realize human detection with encrypted images and efficiently compress the images selected in the image recognition stage.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Software projects mostly exceeds budget, delivered late and does not meet with the customer’s satisfaction for years. In the past, many traditional development models like waterfall, spiral, iterative, and prototyping methods are used to build the software systems. In recent years, agile models are widely used in developing the software products. The major reasons are – simplicity, incorporating the requirement changes at any time, light-weight approach and delivering the working product early and in short duration. Whatever the development model used, it still remains a challenge for software engineer’s to accurately estimate the size, effort and the time required for developing the software system. This survey focuses on the existing estimation models used in traditional as well in agile software development.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Selection of intra prediction modes for intra frame coding in advanced video ...eSAT Journals
Abstract This paper proposes selection of Intra prediction modes for Intra frame coding in Advanced Video Coding Standard using Matlab. The proposed algorithm selects prediction modes for intra frame coding. There are nine prediction modes are there to predict the intra frame in AVC using Intra prediction,but all the prediction modes are not required for all the applications. Intra prediction is the first process of advanced video coding standard. It predicts a macro block by referring to its previous macro blocks to reduce spatial redundancy,appling all the prediction modes to predict intra frame it leads to more computational complexity is increased at the encoder of AVC. In the proposed algoriyhm, applied all the prediction modes(0-8) for prediction of intra frame but only few modes such as mode0, mode1, mode2,mode4,mode6 gives good PSNR, high comprssion ratio and low bit rate. Out of these modes mode2 gives good PSNR, compression ratio and redced bit rate, mode5, mode7 and mode8 gives lower PSNR, low compression ratio and increased bitrate compared to mode0,mode1, mode2, mode4 and mode6. The simulation results are presented using Matlab. The PSNR , compressed ratio and bit rate achived for different quantization parameters of mother daughter frames , foreman frames was presented. Keywords: AVC, PSNR, CAVLC, Macroblock, Prediction modes.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Image type water meter character recognition based on embedded dspcsandit
In the paper, we combined DSP processor with image processing algorithm and studied the
method of water meter character recognition. We collected water meter image through camera
at a fixed angle, and the projection method is used to recognize those digital images. The
experiment results show that the method can recognize the meter characters accurately and
artificial meter reading is replaced by automatic digital recognition, which improves working
efficiency.
An Approach for Iris Recognition Based On Singular Value Decomposition and Hi...paperpublications3
Abstract: This paper presents a new approach using Hidden Markov Model as classifier and Singular Values Decomposition (SVD) coefficients as features for iris recognition. As iris is a complex multi-dimensional structure and needs good computing techniques for recognition and it is an integral part of biometrics. Features extracted from a iris are processed and compared with similar irises which exist in database. The recognition of human irises is carried out by comparing characteristics of the iris to those of known individuals. Here seven state Hidden Markov Model (HMM)-based iris recognition system is proposed .A small number of quantized Singular Value Decomposition (SVD) coefficients as features describing blocks of iris images. SVD is a method for transforming correlated variables into a set of uncorrelated ones that better expose the various relationships among the original data item. This makes the system very fast. The proposed approach has been examined on CASIA database. The results show that the proposed method is the fastest one, having good accuracy.
Improving of Fingerprint Segmentation Images Based on K-MEANS and DBSCAN Clus...IJECEIAES
Nowadays, the fingerprint identification system is the most exploited sector of biometric. Fingerprint image segmentation is considered one of its first processing stage. Thus, this stage affects typically the feature extraction and matching process which leads to fingerprint recognition system with high accuracy. In this paper, three major steps are proposed. First, Soble and TopHat filtering method have been used to improve the quality of the fingerprint images. Then, for each local block in fingerprint image, an accurate separation of the foreground and background region is obtained by K-means clustering for combining 5-dimensional characteristics vector (variance, difference of mean, gradient coherence, ridge direction and energy spectrum). Additionally, in our approach, the local variance thresholding is used to reduce computing time for segmentation. Finally, we are combined to our system DBSCAN clustering which has been performed in order to overcome the drawbacks of K-means classification in fingerprint images segmentation. The proposed algorithm is tested on four different databases. Experimental results demonstrate that our approach is significantly efficacy against some recently published techniques in terms of separation between the ridge and non-ridge region.
Face Recognition Based Intelligent Door Control Systemijtsrd
This paper presents the intelligent door control system based on face detection and recognition. This system can avoid the need to control by persons with the use of keys, security cards, password or pattern to open the door. The main objective is to develop a simple and fast recognition system for personal identification and face recognition to provide the security system. Face is a complex multidimensional structure and needs good computing techniques for recognition. The system is composed of two main parts face recognition and automatic door access control. It needs to detect the face before recognizing the face of the person. In face detection step, Viola Jones face detection algorithm is applied to detect the human face. Face recognition is implemented by using the Principal Component Analysis PCA and Neural Network. Image processing toolbox which is in MATLAB 2013a is used for the recognition process in this research. The PIC microcontroller is used to automatic door access control system by programming MikroC language. The door is opened automatically for the known person according to the result of verification in the MATLAB. On the other hand, the door remains closed for the unknown person. San San Naing | Thiri Oo Kywe | Ni Ni San Hlaing ""Face Recognition Based Intelligent Door Control System"" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-4 , June 2019, URL: https://www.ijtsrd.com/papers/ijtsrd23893.pdf
Paper URL: https://www.ijtsrd.com/engineering/electrical-engineering/23893/face-recognition-based-intelligent-door-control-system/san-san-naing
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implementation of area efficient high speed eddr architectureKumar Goud
Abstract-This project presents an EDDR design, based on the residue-and-quotient (RQ) code, to embed into motion estimation (ME) for video coding testing applications. An error in processing elements (PEs), i.e. key components of a ME, can be detected and recovered effectively by using the EDDR design. The proposed EDDR design for ME testing can detect errors and recover data with an acceptable area overhead and timing penalty. The functional verification and synthesis can be done by Xilinx ISE. That is when compare to the existing design the implemented design area and timing will be reduced.
Index Terms—Area overhead, data recovery, error detection, reliability, residue-and-quotient (RQ) code, Xilinx ISE
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Improved Error Detection and Data Recovery Architecture for Motion Estimation...IJERA Editor
Given the critical role of motion estimation (ME) in a video coder, testing such a module is of priority concern. While focusing on the testing of ME in a video coding system, this work presents an error detection and data recovery (EDDR) design, based on the proposed residue-and-quotient (RQ) code, to embed into ME for video coding testing applications. An error in processing elements (PEs), i.e. key components of a ME, can be detected and recovered effectively by using the proposed EDDR design. Experimental results indicate that the proposed EDDR design for ME testing can detect errors and recover data with an acceptable area overhead and timing penalty. Importantly, the proposed EDDR design performs satisfactorily in terms of throughput and reliability for ME testing applications.
Black Box Model based Self Healing Solution for Stuck at Faults in Digital Ci...IJECEIAES
The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The inherent heal facility attached to the formulation enables to reach out the fault free output even in the presence of faults. The Modelsim based simulation results obtained for the Circuit Under Test [CUT] implemented using a Read Only Memory [ROM], proclaim the ability of the system to survive itself from the influence of faults. The comparison made with the traditional Triple Modular Redundancy [TMR] exhibits the superiority of the scheme in terms of fault coverage and area overhead.
A Novel Approaches For Chromatic Squander Less Visceral Coding Techniques Usi...IJERA Editor
Recent advances in video capturing and display technologies, along with the exponentially increasing demand of
video services, challenge the video coding research community to design new algorithms able to significantly
improve the compression performance of the current H.264/AVC standard. This target is currently gaining
evidence with the standardization activities in the High Efficiency Video Coding (HEVC) project. The distortion
models used in HEVC are mean squared error (MSE) and sum of absolute difference (SAD). However, they are
widely criticized for not correlating well with perceptual image quality. The structural similarity (SSIM) index
has been found to be a good indicator of perceived image quality. Meanwhile, it is computationally simple
compared with other state-of-the-art perceptual quality measures and has a number of desirable mathematical
properties for optimization tasks. We propose a perceptual video coding method to improve upon the current
HEVC based on an SSIM-inspired divisive normalization scheme as an attempt to transform the DCT domain
frame prediction residuals to a perceptually uniform space before encoding.
Based on the residual divisive normalization process, we define a distortion model for mode selection and show
that such a divisive normalization strategy largely simplifies the subsequent perceptual rate-distortion
optimization procedure. We further adjust the divisive normalization factors based on local content of the video
frame. Experiments show that the scheme can achieve significant gain in terms of rate-SSIM performance and
better visual quality when compared with HEVC
A Novel Approaches For Chromatic Squander Less Visceral Coding Techniques Usi...IJERA Editor
Recent advances in video capturing and display technologies, along with the exponentially increasing demand of
video services, challenge the video coding research community to design new algorithms able to significantly
improve the compression performance of the current H.264/AVC standard. This target is currently gaining
evidence with the standardization activities in the High Efficiency Video Coding (HEVC) project. The distortion
models used in HEVC are mean squared error (MSE) and sum of absolute difference (SAD). However, they are
widely criticized for not correlating well with perceptual image quality. The structural similarity (SSIM) index
has been found to be a good indicator of perceived image quality. Meanwhile, it is computationally simple
compared with other state-of-the-art perceptual quality measures and has a number of desirable mathematical
properties for optimization tasks. We propose a perceptual video coding method to improve upon the current
HEVC based on an SSIM-inspired divisive normalization scheme as an attempt to transform the DCT domain
frame prediction residuals to a perceptually uniform space before encoding.
Based on the residual divisive normalization process, we define a distortion model for mode selection and show
that such a divisive normalization strategy largely simplifies the subsequent perceptual rate-distortion
optimization procedure. We further adjust the divisive normalization factors based on local content of the video
frame. Experiments show that the scheme can achieve significant gain in terms of rate-SSIM performance and
better visual quality when compared with HEVC
ALGORITHMIC AND ARCHITECTURAL OPTIMIZATION OF A 3D RECONSTRUCTION MEDICAL IMA...IJCSEIT Journal
This paper presents an optimization of an FPGA circuit implementation of 3D reconstruction algorithm of
medicals images. It is based on an algorithmic specification in the shape of a Factorized and Conditioned
Data Dependences Graph (GFCDD). An automatic and optimized implementation of the algorithm of «
Marching Cubes » has been carried out. The repetitive property of the algorithm has been exploited, as
much as possible, by means of the methodology “Adequacy Algorithm Structures”.
An Efficient Fault Tolerance System Design for Cmos/Nanodevice Digital MemoriesIJERA Editor
Targeting on the future fault-prone hybrid CMOS/Nanodevice digital memories, this paper present two faulttolerance
design approaches the integrally address the tolerance for defect and transient faults. These two
approaches share several key features, including the use of a group of Bose-Chaudhuri- Hocquenghem (BCH)
codes for both defect tolerance and transient fault tolerance, and integration of BCH code selection and dynamic
logical-to-physical address mapping. Thus, a new model of BCH decoder is proposed to reduce the area and
simplify the computational scheduling of both syndrome and chien search blocks without parallelism leading to
high throughput.The goal of fault tolerant computing is improve the dependability of systems where
dependability can be defined as the ability of a system to deliver service at an acceptable level of confidence in
either presence or absence falult.ss The results of the simulation and implementation using Xilinx ISE software
and the LCD screen on the FPGA’s Board will be shown at last.
Fpga implementation of (15,7) bch encoder and decoder for text messageeSAT Journals
Abstract In a communication channel, noise and interferences are the two main sources of errors occur during the transmission of the message. Thus, to get the error free communication error control codes are used. This paper discusses, FPGA implementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each character in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and corrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carried out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrarily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. Finally both encoder and decoder design is implemented on Spartan 3E FPGA. Index Terms: BCH Encoder, BCH Decoder, FPGA, Verilog, Cadence RTL compiler
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
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(IJERA) ISSN: 2248-9622 www.ijera.com
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Implementation of BISDC Architecture in MECA for Video
Coding Applications
D. Rajitha Asst.Prof1
, K. Suresh Asso.Prof2
1, 2 (Department of Electronic Communication & Engineering, Chaitanya Engineering College, JNTUK, VSP-
48
Abstract
This paper develops a built-in self-
detection/correction (BISDC) architecture for
motion estimation computing arrays (MECAs).
Based on the error detection/correction concepts
of biresidue codes, any single error in each
processing element in an MECA can be effectively
detected and corrected online using the proposed
BISD and built-in self-correction circuits.
Performance analysis and evaluation demonstrate
that the proposed BISDC architecture performs
well in error detection and correction with minor
area overhead and timing penalty.
Index Terms - Area overhead, built-in self-
correction (BISC), built-in self-detection (BISD),
motion estimation computing array (MECA).
I. INTRODUCTION
The new Joint Video Team (JVT) video
coding standard has garnered increased attention
recently. Generally, motion estimation computing
array (MECA) performs up to 50% of computations
in the entire video coding system, and is typically
considered the computationally most important part
of video coding systems. Thus, integrating the
MECA into a system-on-chip (SOC) design has
become increasingly important for video coding
applications [1], [2].
Although advances in VLSI technology
allow integration of a large number of processing
elements (PEs) in an MECA into an SOC, this
increases the logic-per-pin ratio, thereby significantly
decreasing the efficiency of chip logic testing. For a
commercial chip, a video coding system must
introduce design for testability (DFT), especially in
an MECA. The objective of DFT is to increase the
ease with which a de-vice can be tested to guarantee
high system reliability. Many DFT ap-proaches have
been developed. These approaches can be divided
into three categories: ad hoc (problem oriented),
structured, and built-in self-test (BIST) [3], [4].
Among these techniques, BIST has an obvious
advantage in that expensive test equipment is not
needed and tests are low cost. Moreover, BIST can
generate test simulations and analyze test responses
without outside support, making tests and diagnoses
of digital systems quick and effective. However, as
the circuit complexity and density increases, the
BIST approach must detect the presence of faults and
specify their locations for subsequent repair. The
extended techniques of BIST are built-in self-
diagnosis [5] and built-in self-re-pair (BISR) [6].
Although BIST and BISR are utilized in many
studies, most studies focused on memory testing.
Nowadays, the computational complexity of modern
video coding systems has increased; thus, effi-cient
self-detection and self-correction techniques are
needed to im-prove reliability.
Based on the concepts of BIST and
biresidue codes, this paper presents a built-in self-
detection/correction (BISDC) architecture that
effectively self-detects and self-corrects PE errors in
an MECA. Notably, any array-based computing
structure, such as the discrete cosine transform
(DCT), iterative logic array (ILA), and finite-impulse
filter (FIR), is suitable for the proposed method to
detect and correct errors based on biresidue codes.
II. ERROR DETECTION/CORRECTION
CODES
The use of residue codes to detect error is a
useful approach in com-puter arithmetic [7]. Residue
codes are separable arithmetic codes that calculate a
residue for data, and then apply this residue to data.
For instance, we assume N denotes an integer, N1
and N2 represent data words, and A is the modulus.
A separate residue code of interest is one in which N
is coded as a pair ( N, |N|A) . Notably, |N|A is the
residue of N modulo A. Error detection logic for
operations is typi-cally derived using a separate
residue code such that detection logic is simply and
easily implemented. However, error correction
cannot be performed effectively using residue codes.
The arithmetic code, namely biresidue codes, can be
supported to realize error detection and error
correction.
The biresidue codes separate residue coding
using two residue detectors with respect to two
suitable moduli. Consider integer N coded as a triple
( N, |N|A, |N|B), where A and B are two rela-tively
prime integers. Let moduli A = 2a
– 1 and 2b
- 1 such
that GCD(a,b) = 1. The set of all single errors
denoted by
2. D. Rajitha, K. Suresh / International Journal of Engineering Research and Applications
(IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.2127-2135
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Fig. 1. Proposed MECA BISDC implementation.
{e=±2i
, i= 0, 1, 2, 3, . . . . . ., n-1} will have distinct
syndromes with respect to A and B provided n is
not greater than ab. Additionally, the triple (X, Y,
Z) is considered a biresidue code word with respect
to moduli A and B if and only if Y=|X|A and
Z=|X|B. Moreover, the syndrome for the triple (X,
Y, Z) with respect to moduli A and B, denoted as
S(X, Y, Z), is a pair (sa, sb) where sa= |X-Y|A and
sb= ||X-Z|B. Thus, a triple (X, Y, Z) of integers is a
biresidue code word with respect to A moduli B
and if and only if its syndrome S(X, Y, Z) with
respect to moduli A and B equals zero (sa = 0, sb
= 0). In other words, the error in any component is
detected and lo-cated based on the form of its
corresponding syndrome. In accordance with the
error detection and error correction concepts in
biresidue codes, this paper proposes a BISDC
architecture to self-detect and self-correct PE errors
in an MECA.
III. PROPOSED METHODOLOGY
To demonstrate the feasibility of the
proposed BISDC architecture, this paper adopts the
MECA as a CUT [8]. The MECA consists of many
PEs connected into a 1-D or 2-D array for video
encoding applications. Generally, a PE is made up
of two adders (an 8-bit adder and 12-bit adder) and
an accumulator. The PE in an MECA computes the
absolute difference between one pixel of the search
area and one pixel of the current macroblock. Thus,
by utilizing PEs, the sum of absolute differences
(SADs) shown in (1) between the current
macroblock and each search position can be
evaluated
N-1 N-1
SAD = ∑ ∑ |c(i, j) – r(i, j)|
(1) i=0 j=0
where c(i, j) and r(i, j) are the luminance pixel
value of current pixel (Cur.pixel) and reference
pixel (Ref.pixel), respectively. The macroblock size
is N x N. The 2-D H.264/Advanced Video Coding
(AVC) motion estimation architecture published in
[9] is a clear example of MECA operations. The
best motion position of a 4 x 4 block from the
previous frame to the current frame can be captured
easily using MECA operations in the video
encoding system.
According to MECA characteristics, Fig.1
shows the corresponding BISDC implementation.
Signals TC1 and TC2 are utilized to select
datapaths from Cur.pixel and Ref.pixel,
respectively. The output of a specific PEi can be
delivered to a detector for detecting errors using the
DC1 signal. Moreover, the selector circuit is
controlled by signals SC1 and SC2 that receive
data from a specific PEi, and then export these data
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to the next specific PEi+1 or syndrome analysis and
corrector (SAC) for error correction. The self-
detection and self-correction operations (Fig. 1) are
simply described as follows.
Fig. 2. Example of the self-detection/correction operations
Fig. 3. Block diagram of a coder.
Selector circuit in DAS delivers the error
signal to SAC for error correction. Finally, the error
correction data from SAC, or error-free data from the
selector circuit in DAS, are passed to the next
specific PEi+1 for subsquent testing.
B. Fault Model
The PEs are important builiding blocks and
are connected in a regular manner to construct an
MECA. Generally, Pes are surrounded by set of
adders and accumulators that determine how data
flows through them. Thus, Pes can be considered the
class of circuits called ILAs, whose testing
assignment can be easily achieved using the fault
model called as cell fault model (CFM) [10]. The use
of the CFM is currently of considerable interest due
to the rapid growth in the use of high-level synthesis
and the parallel increasing complexity and density of
Ics. Using the CFM allows tests to be independent of
the adopted synthesis tool and vendor library.
Arithmetic modules, like adders (the primary element
in a PE), due to their regularity, are designed in a
very dense configuration.
Moreover, the use of a relatively more
comprehensive fault model, the single stuck –at
(SSA) model, is required to cover actual failures in
the interconnected databus between PEs. The SSA
fault is a well-known structural fault model that
assumes faults cause a line in the circuit to bahave as
it work permenantly at logic “0” [stuck-at 0 (SA0)] or
logic “1” [stuck-at 1 (SA1)]. The SSA fault in an
MECA architecture can result in errors in computed
SAD values. This paper refers to this as a distorted
computational error; its magnitude is e = SAD‟ –
SAD , where SAD1 is the computed SAD value with
an SSA fault.
C. BISDC Processes
Fig.2 shows an example of a specific PE, to
describe explicitly the self-detection and self-
correction of errors in an MECA using the proposed
BISDC architecture. The TCG circuit uses two
4. D. Rajitha, K. Suresh / International Journal of Engineering Research and Applications
(IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.2127-2135
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coders (coders φ1 and φ2) to generate test codes. The
following definitions, based on the biresidue codes,
are applied to verify the feasibility of the two coders
in the TCG.,
Definition 1:
| N1 +N2|φ = ||N1|φ + |N2|φ|φ . (2)
Definition 2: Let Nj = n1 + n2 + n3 + …..+nj, then
| Nj|φ = ||n1|φ +| n2|φ + |n3|φ+ …..+ |nj|φ|φ . (3)
Based on the definitions 1 and 2, the design of the
coder φ1 (or coder φ2) circuit can be realized and
shown in fig.3.
Fig.4 shows the timing chart for a specific
PEi in an MECA to describe the operation of coder
φ1 circuit in the TCG. If data n1 and n2, obtained
from Cur.pixel and Ref.pixel, are sent to the Modφ11
and Modφ12 circuits at the first clock, then values
|n1|φ1 and |n2|φ1 can be treated at the second clock.
When the third clock is triggered, the summation of
modulus values, α = |n1|φ1+ |n2|φ1, is generated by the
adder. Additionally, the following two data, n3 and n4,
are simultaneously passed into the Modφ11 and
Modφ12 circuits for modulo operations. The Modφ13
circuit executes the operation of |α|φ1 = ||n1|φ1+|n2|φ1
|φ1, and then stores the computational results in the
register at the fourth clock. Moreover, the summation
of the modulus value β = | n3|φ1 +| n3|φ1 can be
captured by an adder at this time. Notably, the two
selected signals S1 and S2 in multiplexers M1 and M2
are set to 0 to sum the modulus values at clocks 1 – 4.
At the fifth clock, the next two data, n5 and n6, are
transmitted to the coder φ1 circuit, and signals S1 and
S2 are changed from 0 to 1 to deliver the values of
|α|φ1 and |β|φ1 to the adder for addition. Fig.4 clearly
demonstrates that the regularity processes will
continue after the fifth clock. Since a 4 x 4
macroblock in a specific PEi of the MECA contains
16 pixels, the accumulated input data from coder φ1
and coder φ2 circuits in the TCG are exported to the
DAC and SAC circuits for error detection and error
correction, respectively, after 50clocks.
Fig. 4. Timing chart of a coder circuit
TABLE 1
SYNDROME CORRESPONDING TO ALL SINGLE BOT ERRORS
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1) Self-Detection Operation: The self-detection
operation can be achieved using the DAS circuit. The
detector circuit is utilized to com-pare the outputs
between a specific PEi and the TCG for determining
whether an error has occurred (Fig. 2). A selector
circuit in DAS is then enabled to place the error in
the SAC circuit for error correction or to export the
error-free results to the output directly.
A mathematical statement is presented
herein to verify the self-de-tection operation.
According to Definition 2, the residue of the Nj
modulo φ is | Nj|φ = ||n1|φ +| n2|φ + |n3|φ+ …..+
|nj |φ|φ when the specific PEi has j pixels. Moreover,
based on the biresidue codes theorem, a triple (Nj, X,
Y) with respect to moduli φ1 and φ2 is given by
X = | Nj|φ1 = ||n1|φ1 +| n2|φ1 + |n3|φ1+ …..+ |nj |φ1|φ1 (4)
Y = | Nj|φ2 = ||n1|φ2 +| n2|φ2 + |n3|φ2+ …..+ |nj |φ2|φ2 (5)
Thus, the syndrome can be represented by the pair
(sφ1 = |Nj – X|φ1, sφ2 = |Nj – X|φ2 ). Additionally, we
assume the pixel value is adjusted to |N‟j| = Nj + e
when an error bit is present in the specific PEi.
According to Definition 2, the residue of N‟j modulo
φ1 and φ2 is given by
|N‟j|φ1 = | Nj + e|φ1 = ||Nj|φ1 + |e|φ1|φ1 (6)
|N‟j|φ2 = | Nj + e|φ2 = ||Nj|φ2 + |e|φ2|φ2 (7)
Thus, the single error bit in the specified PEi can be
detected if and only if (4) ≠ (6) and/or (5) ≠ (7).
2) Self-Correction Operation: In the self-correction
operation, the SAC circuit plays an important role in
correcting errors in a specific PEi. The SAC circuit
(Fig. 2) receives data from the TCG and DAS circuits
to start error correction. The syndrome decoder and
corrector circuits in the SAC are employed to
diagnose single error and further correct error signal,
respectively. In other words, the syndrome decoder in
the SAC generates syndromes sφ1and sφ2 by adopting
the error correction concepts of biresidue codes.
Table I and Fig. 5 show the syndromes corresponding
to all cases of single bit error and the corrector
circuit, respectively, i.e., any single bit error of a
specific PEi of the MECA can be obtained by
comparing the syndrome (sφ1, sφ2) with Table I, and
then the bit error is corrected using the circuit in Fig.
5.
For instance, based on (4)–(7), syndromes
sφ1and sφ2 can be ex-pressed as
(sφ1, sφ2) = (|N‟j – X|φ1 , |N‟j – Y|φ2) = (|e|φ1, |e|φ2). (8)
Here, the specific PEi is error-free when the
syndrome (sφ1, sφ2) = (0, 0). However, a single error
bit can be detected when the syndrome (sφ1, sφ2) ≠ (0,
0), and the error bit can be located and corrected
using the syndrome listed in Table I and the circuit
shown in Fig. 5.
IV. PERFORMANCE EVALUATION
The proposed BISDC architecture was
generated using VHDL and synthesized using the
Synopsys Design Compiler with TSMC 0.18 m
1P6M CMOS technology. The MECA was selected
to act as the CUT to demonstrate the effectiveness of
the proposed BISD and built-in self-correction
(BISC) procedures. The area overhead, timing
penalty, and throughput are also utilized to
demonstrate the good performance of the proposed
BISDC architecture.
Fig. 5. Circuit of corrector in SAC.
6. D. Rajitha, K. Suresh / International Journal of Engineering Research and Applications
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Table II summarizes synthesis results of area
estimation of the circuit design. The area is estimated
based on the number of cells. Considering 16 PEs in
an MECA, the area overhead introduced is given by
AREAOVERHEAD=
𝐴𝑅𝐸𝐴BISD +𝐴𝑅𝐸𝐴𝐵𝐼𝑆𝐶 −𝐴𝑅𝐸𝐴𝑇𝐶𝐺
𝐴𝑅𝐸𝐴𝑀𝐸𝐶𝐴
(9)
The self-detection and self-correction
functionalities can be achieved using the proposed
BISD and BISC with about 0.86% and 2.44% area
overhead, respectively (Table II). Based on (9), Table
II also shows the total area overhead of the proposed
BISDC architecture, only 2.80%, which is reasonable
for designing a circuit for testing. The timing penalty
and throughput must also be demonstrated to verify
the flexibility of the proposed BISDC architecture.
Table III shows the operating time estimation of a
specific and each component in the proposed BISDC
architecture. Each in an MECA is tested in
succession; thus, a 4 2 4 macroblock (with 16 pixels)
is used to estimate timing penalty. A specific requires
1313.76 and 1328.95 ns for self-detection and self-
correction operations, respectively (Table III).
Notably, the proposed BISDC architecture is a
noncurrent online testing scheme for error
detection/correction of faulty PEs. In other words, an
error detection/correction operation for each faulty
PE in an MECA is executed in sequence. Thus, if the
pro-posed BISDC architecture is embedded into the
MECA for testing, the entire timing penalty is equal
to that for testing a single PE, i.e., about 1.55% and
2.72% (Table III) for BISD and BISC, respectively.
TABLE II
AREA OVERHEAD ESTIMATION
TABLE III
TIMING PENALTY AND THROUGHPUT ESTIMATION
The test processes for the TCG circuit
and tested are operated in parallel (Fig. 2).
Preparation time of the TCG circuit is faster than that
of the one-pixel operation of the tested (Table III).
Therefore, the operation time of the TCG circuit can
be neglected because the timing penalty of the TCG
is covered by the pixel operation. Table III also
shows the total number of accessing macroblocks per
second. Obviously, when the MECA is combined
with the proposed BISDC architecture, complexity
and throughput will be increased and decreased,
respectively, i.e., complexity increases to 2.6% when
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an error occurs. Although the throughput of the
MECA with the proposed BISDC architecture is
lower than that of the MECA without the BISDC
architecture, fewer data access is indicative of
reduced demand on input/output bandwidth.
Generally, a low memory bandwidth is desirable in
the progressive high-definition television (HDTV)
video format.
V. RESULTS
Simulation results of Absolute Difference
Absolute Difference as a two inputs a, b i.e.
current and reference pixels each of 8-bit length and
one output result also 8-bit length. The behavioral
simulation waveform for the Absolute Difference.
The two inputs with 8-bit length are „a‟ (current
Pixels) and „b‟ (reference pixels) and 8-bit output
result.
Fig 6: Simulation Waveform for Absolute difference
Simulation Results of Compressor Module
Compressor Module as a two inputs a, b
each of 8-bit length and one output c also 8-bit
length. The behavioral simulation waveform for the
Compressor. The two inputs with 8-bit length are „a‟
(current Pixels) and „b‟ (reference pixels) and 8-bit
output.
Fig 7:Simulation Waveform of compressor
Simulation waveforms of Processing Element
module
Processing Element as a three inputs
create_error, current pixel, reference pixel each of 8-
bit and output is a sad_dash as a 12-bit data. The
input of PE is a current pixel and reference pixels.
The behavioral simulation waveform for the
Processing Element. The two inputs are 8-bit length
are „a‟ (current Pixels) and „b‟ (reference pixels)
input and 12-bit output.
Fig 8:Simulation Waveform of Processing Element
Simulation Results of Modulus code
Modulus code as a two inputs i.e. dividend,
divider each of 12-bit length and it has one output it
as a modulus 4 –bit of length. The behavioral
simulation waveform for the Modulus Division code
as a two inputs i.e. dividend, divider each of 12-bit
length and it has one output it as a modulus 4 –bit of
length.
Fig 9:Simulation Waveform of Modulus
Simulation Results of Coder module :
Coder as a three inputs clk, cur_pix, ref_pix
and each of 8-bit length and output consists two
coders i.e. out_a, out_b it consists of 4-bit length. The
input of a coder is clk, current and reference pixels.
The behavioral simulation waveform for the Coder as
a three inputs clk, cur_pix, ref_pix and each of 8-bit
length and output consists two coders i.e. out_a,
out_b it consists of 4-bit length. The input of a coder
is clk, current and reference pixels.
Fig10: Simulation Waveform of Coder
Simulation Results of Selector Module:
Selector takes the output of the PE as an
input. Another input to the selector is the output of
the detector. It has three inputs clk, select, PE_out.
And the output is select_out, error_free each of 12-bit
length. The behavioral simulation waveform for the
Selector takes the output of the PE as an input.
8. D. Rajitha, K. Suresh / International Journal of Engineering Research and Applications
(IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.2127-2135
2134 | P a g e
Another input to the selector is the output of the
detector. It has three inputs clk, select, PE_out. And
the output is select_out, error_free each of 12-bit
length.
Fig 11:Simulation Waveform of Selector
Simulation results of Corrector Module:
Input to the Corrector module is the output
of the selector module which is SAD that needs to be
corrected. It as three inputs select_out, sphi_1, sphi_2
and output as a corr_out as a12-bit length. The
behavioral simulation waveform for the Input to the
Corrector module is the output of the selector module
which is SAD that needs to be corrected. It as three
inputs select_out, sphi_1, sphi_2 and output as a
corr_out as a12-bit length.
Fig12:simulation waveform of Corrector
Simulation results of Top Module
The proposed design is developed in a top
down design methodology that the code is a mixed
version of both behavioral and structural. The
proposed Architecture consists of basic modules like
Absolute Difference, Compressor, Processing
Element, Modulus Division, Coder, Selector and
Corrector modules. The behavioral simulation results
for Top Module i.e., BISDC Architecture for MECA
with inputs of clk, cur_pixel[7:0], ref_pixel[7:0],
Create_error and outputs with error, with_out_error
are given in Fig 7.16. This waveform contains signals
like N (sum of total number of current pixels and
reference pixels without error), N_dash_error (sum of
total number of current pixels and reference pixels
with error), syndrome_7 [3:0], syndrome_15 [3:0].
Current pixels:
5,15,45,20,23,12,15,24,11,55,15,25,15,77,30,20
Reference pixels:
9,19,35,24,19,10,30,20,49,9,9,19,69,74,10,50
N=n1+n2+n3+………………………………………
….……..n32
N =
5+9+15+19+45+35+20+24+23+19+12+10+15+30+2
4+20+11+49+55+9+15+9+25+
19+15+69+77+74+30+10+20+30
N = 862
Sum of Absolute Difference (SAD) =
4+4+10+4+4+2+15+4+38+46+6+6+54+3+20+30
Sum of Absolute Difference = 250
e=SAD‟-SAD=1 (error should create)
Where SAD‟=Sum of absolute difference of with
error
SAD‟=251
N_dash = N+1 = 862+1=863.
Fig 13 : Simulation waveform of Top module
VI. CONCLUSION
This paper proposes a BISDC architecture
for self-detection and self-correction of errors of PEs
in an MECA. Based on the error de-tection/correction
concepts of biresidue codes, this paper presents the
corresponding definitions used in designing the BISD
and BISC cir-cuits to achieve self-detection and self-
correction operations.
Perfor-mance evaluation reveals that the
proposed BISDC architecture effec-tively achieves
self-detection and self-correction capabilities with
min-imal area overhead and a small timing penalty.
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